Electrical and Thermal Characteristics
Figure 8 provides the JTAG clock input timing diagram.
TCLK
VM
VM
VM
tJHJL
tJR
tJF
tTCLK
VM = Midpoint Voltage (OVDD/2)
Figure 8. JTAG Clock Input Timing Diagram
Figure 9 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 9. TRST Timing Diagram
Figure 10 provides the boundary-scan timing diagram.
TCK
Boundary
Data Inputs
Boundary
Data Outputs
VM
tJLDV
tJLDX
tDVJH
VM
Input
Data Valid
tDXJH
Output Data Valid
Boundary
Data Outputs
tJLDZ
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 10. Boundary-Scan Timing Diagram
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor