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MPC7447A

RISC Microprocessor Hardware Specifications

Freescale Semiconductor 

Electrical and Thermal Characteristics

Table 9. Processor Bus AC Timing Specifications1 (continued)

At recommended operating conditions. See Table 4.

Parameter

All Speed Grades

Symbol 2

Unit Notes

Min

Max

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

tKHARPZ

—

precharge

2

tSYSCLK 3, 5, 6, 7

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to

the midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input

and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and

connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs

and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid

state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV

symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold

time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)

(note the position of the reference and its state for inputs) and output hold time can be read as the time from the

rising edge (KH) until the output went invalid (OX).

3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by

the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and

precharged high before returning to high impedance, as shown in Figure 6. The nominal precharge width for TS

is 0.5 × tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on

the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately

following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any

master asserting it low in the first clock following AACK will then go to high impedance for 1 clock before

precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY

is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another

master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance

behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle

of TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated

for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge

width for SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio

of core to bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These

parameters represent the input setup and hold times for each sample. These values are guaranteed by design

and not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing.

Figure 4 provides the AC test load for the MPC7447A.

Output

Z0 = 50 Ω

RL = 50 Ω

OVDD/2

Figure 4. AC Test Load

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

17

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