Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7447A. The mode select inputs are
sampled twice, once before and once after HRESET negation.
SYSCLK
VM
VM
HRESET
Mode Signals
1st Sample
2nd Sample
VM = Midpoint Voltage (OVDD/2)
Figure 5. Mode Input Sample Timing Diagram
Figure 6 provides the input/output timing diagram for the MPC7447A.
SYSCLK
VM
All Inputs
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
tKHOE
tAVKH
tIVKH
tMVKH
tKHAV
tKHDV
tKHOV
tKHTSV
TS
VM
tAXKH
tIXKH
tMXKH
tKHAX
tKHDX
tKHOX
tKHOZ
tKHTSPZ
tKHTSV
tKHTSX
ARTRY,
SHD0,
SHD1
tKHARV
tKHARP
tKHARX
VM = Midpoint Voltage (OVDD/2)
Figure 6. Input/Output Timing Diagram
VM
tKHARPZ
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
18
Freescale Semiconductor