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MPC7447A

RISC Microprocessor Hardware Specifications

Freescale Semiconductor 

Figure 11 provides the test access port timing diagram.

Electrical and Thermal Characteristics

TCK

TDI, TMS

TDO

VM

tJLOV

tJLOX

VM

tIVJH

Input

Data Valid

tIXJH

Output Data Valid

TDO

tJLOZ

Output Data Valid

VM = Midpoint Voltage (OVDD/2)

Figure 11. Test Access Port Timing Diagram

5.3 Voltage and Frequency Derating

To reduce the power consumption of the device, these devices support voltage and frequency derating

whereby the core voltage (VDD) may be reduced if the reduced maximum processor core frequency

requirements are observed. The supported derated core voltage, resulting maximum processor core

frequency (fcore), and power consumption are provided in Table 11. Only those parameters in Table 11 are

affected; all other parameter specifications are unaffected.

Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating

Maximum Rated

Core Frequency

(Device Marking)

Supported

Derated Core

Voltage (VDD)

Maximum Derated Core

Frequency (fcore)

Full-Power Mode Power

Consumption

Maximum

Typical

1000

1267

1333

1420

1.20 V ±50mV

867 MHz

1065 MHz

1167 MHz

1267 MHz

15.5 W

18.2 W

18.1 W

21.0 W

10.5 W

12.3 W

12.3 W

14.2 W

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

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