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PTN3460

eDP to LVDS bridge IC

NXP Semiconductors. 

NXP Semiconductors

PTN3460

eDP to LVDS bridge IC

8.3.4 Termination resistors

The device provides integrated and calibrated 50  termination resistors on both

DisplayPort Main Link lanes and AUX channel.

8.3.5 Reference clock input

PTN3460 does not require an external clock. It relies fully on the clock derived internally

from incoming DP stream or on-chip clock generator.

8.3.6 Power supply

PTN3460 can be flexibly supplied with either 3.3 V supply only or dual supplies

(3.3 V/1.8 V). When supplied with 3.3 V supply only, the integrated regulator is used to

generate 1.8 V for internal circuit operation. In this case, the EPS_N pin must be pulled

HIGH or left open. For optimal power consumption, dual supply option (3.3 V and 1.8 V) is

recommended.

8.3.7 Power management

In tune with the system application needs, PTN3460 implements aggressive techniques to

support system power management and conservation. The device can exist in one of the

three different states as described below:

• Active state when the device is fully operational.

• Low-power state when DP source issues AUX SET_POWER command on DPCD

register 00600h. In this state, AUX and HPD circuits are operational but the main

DP Link and LVDS Bus are put to high-impedance condition. The device will transition

back to Active state when the DP source sets the corresponding DPCD register bits to

‘DisplayPort D0/Normal Operation mode’. The I2C-bus interface will not be

operational in this state.

• Deep power-saving state: In this state PTN3460 is put to ultra low-power condition.

This is effected when PD_N is LOW. To get back to Active state, PD_N must be made

HIGH. The external interfaces (like I2C, AUX, DP, LVDS, configuration pins) will not be

operational.

8.3.8 Register interface — control and programmability

PTN3460 has a register interface that can be accessed by CPU/GPU or System

Controller to choose settings suitably for the System application needs. The registers can

be read/written either via DP AUX or I2C-bus interface. It is left to system integrator choice

to use an interface to configure PTN3460.

PTN3460 provides greater level of configurability of certain parameters (e.g., LVDS output

swing, spreading depth, etc.) via registers beyond what is available through pins. The

register settings override the pin values. All registers must be configured during power-on

initialization after HPDRX is HIGH. The registers and bit definitions are described in

“I2C-bus utility and programming guide for firmware and EDID update” (Ref. 3).

8.3.9 EDID handling

The DP source issues EDID reads using I2C-over-AUX transactions and PTN3460, in

turn, reads from the panel EDID ROM and passes back to the source. To support

seamless functioning of panels without EDID ROM, the PTN3460 can be programmed to

emulate EDID ROM and delivers internally stored EDID information to the source. Given

PTN3460

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 12 March 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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