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PTN3460 Datasheet PDF : 32 Pages
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NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
12.3 DisplayPort receiver characteristics
Table 18. DisplayPort receiver main channel characteristics
Over operating free-air temperature range (unless otherwise noted).
Symbol
Parameter
Conditions
UI
unit interval
high bit rate
(2.7 Gbit/s per lane)
reduced bit rate
(1.62 Gbit/s per lane)
fDOWN_SPREAD
CRX
VRX_DIFFp-p
link clock down spreading
AC coupling capacitor
differential input peak-to-peak
voltage
at receiver package pins
high bit rate
(2.7 Gbit/s per lane)
reduced bit rate
(1.62 Gbit/s per lane)
VRX_DC_CM
IRX_SHORT
fRX_TRACKING_BW
Geq(max)
RX DC common mode voltage
RX short-circuit current limit
jitter tracking bandwidth
maximum equalization gain
at 1.35 GHz
Min
Typ
Max
[1] -
370 -
[1] -
617 -
[2] 0
-
0.5
75
-
200
[3] 120
-
-
[3] 40
-
-
[4] 0
-
2.0
[5] -
-
50
[6] 20
-
-
-
15
-
[1] Range is nominal 350 ppm. DisplayPort channel RX does not require local crystal for channel clock generation.
[2] Up to 0.5 % down spreading is supported. Modulation frequency range of 30 kHz to 33 kHz is supported.
[3] Informative; refer to Figure 6 for definition of differential voltage.
[4] Common-mode voltage is equal to Vbias_RX voltage.
[5] Total drive current of the input bias circuit when it is shorted to its ground.
[6] Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.
Unit
ps
ps
%
nF
mV
mV
V
mA
MHz
dB
VD+
VCM
VD−
VDIFF_PRE VDIFF
pre-emphasis = 20Log(VDIFF_PRE / VDIFF)
Fig 6. Definition of pre-emphasis and differential voltage
002aaf363
PTN3460
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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