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Fabricante

PTN3460

eDP to LVDS bridge IC

NXP Semiconductors. 

NXP Semiconductors

PTN3460

eDP to LVDS bridge IC

8.3.3 Panel power sequencing

Figure 4 illustrates an example of panel power-up/power-down sequence for PTN3460.

Depending on the source behavior and PTN3460 firmware version, the powering

sequence/timing could have some slight differences.

VDD(3V3)

LCDVCC

PVCCEN

LVDS interface

SINK_STATUS

HPDRX

eDP AUX channel

eDP Main Link

display backlight

T2 < 50 ms

black video

from PTN3460

video from source

T12 > 500 ms

T5 < 50 ms

Link Training

idle

disabled

AUX channel operational

valid video data

enabled

video or IDLE stream

from DP source

T3 > 200 ms

to 1000 ms

T4 > 200 ms

002aaf839

Fig 4.

T2: Time interval between panel power enable signal (PVCCEN) going HIGH and video data/clock driven on LVDS interface.

T3: Time interval between valid video data/clock on LVDS interface and backlight enable signal (BKLTEN) going HIGH.

T4: Time interval between backlight enable signal (BKLTEN) made LOW and stopping of video data/clock on LVDS interface.

T5: Time interval between stopping of video data/clock on LVDS interface and panel power enable signal (PVCCEN) made

LOW.

T12: Time interval for which PVCCEN is held LOW before it can be made HIGH.

Panel power-up/power-down sequence example

PTN3460

Product data sheet

When working with eDP capable DP sources, PTN3460 supports the following (for

specific sequence, refer to Figure 4):

• After power-on/startup, HPDRX is asserted HIGH, DP source will start AUX

communication for initialization, perform Link Training and starts the video data

stream. Once presence of video data is detected, PTN3460 will assert PVCCEN to

HIGH, synchronize to video stream, output LVDS data and assert rise the Sink_status

lock as indicated in DPCD register (0x00205h). PTN3460 will wait for Backlight

enabling delay (T3) to avoid visual artifacts and program the BKLTEN HIGH.

• While transitioning out of Active state by receiving DPCD 0x600 to set PTN3460 in

D3 mode, PTN3460 will disable BKLTEN prior to cutting off Video streaming to avoid

visible artifacts following specific panel specifications. PTN3460 will assert PVCCEN

to LOW after T5 delay as long as either if the video stream is stopped or video

synchronization is lost. This is to avoid driving the LVDS panel with illegal stream for

long periods of time. It is good practice for sources to keep video data or at least

DP-idle stream active during T4 + T5.

• When PTN3460 is in Low-power state (DisplayPort D3 power state), the LVDS

differential I/Os are weakly pulled down to 0 V. In this state, PVCCEN and BKLTEN

are pulled LOW.

• When PD_N is LOW, which sets PTN3460 in Deep power-saving state, the BKLTEN

pin is set to LOW. LVDS differential I/Os are pulled LOW via the weak pull-downs.

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 12 March 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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