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PTN3460 Datasheet PDF : 32 Pages
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NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
Table 11. LVDS single bus, 24 bpp, JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LVDS odd differential channel B
bit 3
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 7
bit 6
bit 5
bit 4
LVDS odd differential channel D
don’t care bit 1
bit 0
bit 1
bit 0
bit 1
bit 0
Table 12. LVDS dual bus, 18 bpp, JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS odd differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS even differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS even differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
Table 13. LVDS dual bus, 24 bpp, JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LVDS odd differential channel B
bit 3
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 7
bit 6
bit 5
bit 4
LVDS odd differential channel D
don’t care bit 1
bit 0
bit 1
bit 0
bit 1
bit 0
LVDS even differential channel A
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel B
bit 3
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
LVDS even differential channel C
DE
VSYNC HSYNC
bit 7
bit 6
bit 5
bit 4
LVDS even differential channel D don’t care bit 1
bit 0
bit 1
bit 0
bit 1
bit 0
PTN3460 delivers great flexibility by supporting more programmable options via I2C-bus
or AUX interface. Please refer to Section 8.3.8 for more details.
PTN3460
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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