CS8900-CQ Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Fabricante

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

the CS8900 provides the capability to switch be-

tween Memory or I/O operation and DMA

operation by using Auto-Switch DMA and

StreamTransfer.

Sections 5.2 through 5.6 provide a detailed de-

scription of packet reception.

3.2 ISA Bus Interface

The CS8900 provides a direct interface to ISA

buses running at clock rates from 8 to 11 MHz.

Its on-chip bus drivers are capable of delivering

24 mA of drive current, allowing the CS8900 to

drive the ISA bus directly, without added exter-

nal "glue logic".

The CS8900 is optimized for 16-bit data trans-

fers, operating in either Memory space, I/O

space, or as a DMA slave.

Note that ISA-bus operation below 8 MHz

should use the CS8900’s Receive DMA mode to

minimize missed frames. See Section 5.4 for a

description of Receive DMA operation.

Memory Mode Operation

When configured for Memory Mode operation,

the CS8900’s internal RAM is mapped into a

contiguous 4-Kbyte block of host memory, pro-

viding the host with direct access to the

CS8900’s internal registers and frame buffers.

The host initiates Read operations by driving the

MEMR pin low and Write operations by driving

the MEMW pin low.

For additional information about Memory Mode,

see Section 4.9.

I/O Mode Operation

When configured for I/O Mode operation, the

CS8900 is accessed through eight, 16-bit I/O

ports that are mapped into sixteen contiguous

I/O locations in the host system’s I/O space. I/O

Mode is the default configuration for the

CS8900 and is always enabled.

For an I/O Read or Write operation, the AEN pin

must be low, and the 16-bit I/O address on the

ISA System Address bus (SA0 - SA15) must

match the address space of the CS8900. For a

Read, IOR must be low, and for a Write, IOW

must be low.

For additional information about I/O Mode, see

Section 4.10.

Interrupt Request Signals

The CS8900 has four interrupt request output

pins that can be connected directly to any four of

the ISA bus Interrupt Request signals. Only one

interrupt output is used at a time. It is selected

during initialization by writing the interrupt

number (0 to 3) into PacketPage Memory base +

0022h. Unused interrupt request pins are placed

in a high-impedance state. The selected interrupt

request pin goes high when an enabled interrupt

is triggered. The pin goes low after the Interrupt

Status Queue (ISQ) is read as all 0’s (see Section

5.1 for a description of the ISQ).

CS8900 Interrupt

Request Pin

INTRQ3 (Pin 35)

INTRQ0 (Pin 32)

INTRQ1 (Pin 31)

INTRQ2 (Pin 30)

ISA Bus

Interrupt

IRQ5

IRQ10

IRQ11

IRQ12

PacketPage

base + 0022h

0003h

0000h

0001h

0002h

Table 3.1. Interrupt Assignments

14

DS150PP2

Share Link: