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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview

During normal operation, the CS8900 performs

two basic functions: Ethernet packet transmis-

sion and reception. Before transmission or

reception is possible, the CS8900 must be con-

figured.

Configuration

The CS8900 must be configured for packet

transmission and reception at power-up or reset.

Various parameters must be written into its inter-

nal Configuration and Control registers such as

Memory Base Address; Ethernet Physical Ad-

dress; what frame types to receive; and which

media interface to use. Configuration data can

either be written to the CS8900 by the host

(across the ISA bus), or loaded automatically

from an external EEPROM. Operation can begin

after configuration is complete.

Sections 3.1 and 3.3 describe the configuration

process in detail. Section 4.4 provides a detailed

description of the bits in the Configuration and

Control Registers.

Packet Transmission

Packet transmission occurs in two phases. In the

first phase, the host moves the Ethernet frame

into the CS8900’s buffer memory. The first

phase begins with the host issuing a Transmit

Command. This informs the CS8900 that a

frame is to be transmitted and tells the chip

when (i.e. after 5, 381, or 1021 bytes have been

transferred, or after the full frame has been trans-

ferred to the CS8900) and how the frame should

be sent (i.e. with or without CRC, with or with-

out pad bits, etc.). The Host follows the Transmit

Command with the Transmit Length, indicating

how much buffer space is required. When buffer

space is available, the host writes the Ethernet

DS150PP2

frame into the CS8900’s internal memory, either

as a Memory or I/O space operation.

In the second phase of transmission, the CS8900

converts the frame into an Ethernet packet then

transmits it onto the network. The second phase

begins with the CS8900 transmitting the pream-

ble and Start-of-Frame delimiter as soon as the

proper number of bytes has been transferred into

its transmit buffer (5, 381, 1021 bytes or full

frame, depending on configuration). The pream-

ble and Start-of Frame delimiter are followed by

the Destination Address, Source Address, Length

field and LLC data (all supplied by the host). If

the frame is less than 64 bytes, including CRC,

the CS8900 adds pad bits if configured to do so.

Finally, the CS8900 appends the proper 32-bit

CRC value.

Section 5.7 provides a detailed description of

packet transmission.

Packet Reception

Like packet transmission, packet reception oc-

curs in two phases. In the first phase, the

CS8900 receives an Ethernet packet and stores it

in on-chip memory. The first phase of packet re-

ception begins with the receive frame passing

through the analog front end and Manchester de-

coder where Manchester data is converted to

NRZ data. Next, the preamble and Start-of-

Frame delimiter are stripped off and the receive

frame is sent through the address filter. If the

frame’s Destination Address matches the criteria

programmed into the address filter, the packet is

stored in the CS8900’s internal memory. The

CS8900 then checks the CRC, and depending on

the configuration, informs the processor that a

frame has been received.

In the second phase, the host transfers the re-

ceive frame across the ISA bus and into host

memory. Receive frames can be transferred as

Memory space operations, I/O space operations,

or as DMA operations using host DMA. Also,

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