CS8900-CQ Ver la hoja de datos (PDF) - Cirrus Logic
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CS8900-CQ Datasheet PDF : 132 Pages
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CS8900
(Register 16, SelfST, bit 8) to clear. After each
command has been issued, the host must wait
again for SI-BUSY to clear.
Enabling Access to the EEPROM
The Erase/Write Enable command provides pro-
tection from accidental writes to the EEPROM.
The host must write an Erase/Write Enable com-
mand before it attempts to write to or erase any
EEPROM memory location. Once the host has
finished altering the contents of the EEPROM, it
must write an Erase/Write Disable command to
prevent unwanted modification of the EEPROM.
Writing and Erasing the EEPROM
To write data to the EEPROM, the host must
execute the following series of commands:
AD7 - AD0 used with ’C56,
’CS56, ’C66 and ’CS66
F EDCB A
9876543210
X X X X X ELSEL OB1 OB0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Bit
[F:B]
[A]
[9:8]
[7:0]
AD5 - AD0 used with
’C46 and ’CS46
Name
Description
Reserved
ELSEL
OB1, OB0
External Logic Select: When clear, the EECS pin is used to select the EEPROM. When set,
the ELCS pin is used to select the external LA decode circuit.
Opcode: Indicates what command is being executed (see next section).
AD7 to AD0 EEPROM Address: Address of EEPROM word being accessed.
Figure 3.2. EEPROM Command Register Format
Command
Read Register
Write Register
Erase Register
Erase/Write Enable
Opcode
(bits 9,8)
1,0
0,1
1,1
0,0
Erase/Write Disable
0,0
0,0
Erase-All Registers
0,0
0,0
Write-All Registers
0,0
0,0
EEPROM Address
(bits 7 to 0)
word address
word address
word address
XX11-XXXX
11XX-XXXX
XX00-XXXX
00XX-XXXX
XX10-XXXX
10XX-XXXX
XX01-XXXX
01XX-XXXX
Data
yes
yes
no
no
no
no
no
no
no
yes
yes
EEPROM
Type
all
all
all
’CS46, ’C46
’CS56, ’C56, ’CS66, ’C66
’CS46, ’C46
’CS56, ’C56, ’CS66, ’C66
’CS46, ’C46
’CS56, ’C56, ’CS66, ’C66
’CS46, ’C46
’CS56, ’C56, ’CS66, ’C66
Table 3.7. EEPROM Commands
DS150PP2
Execution
Time
25 µs
10 ms
10 ms
9 µs
9 µs
9 µs
9 µs
10 ms
10 ms
10 ms
10 ms
21
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