UPD16498 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD16498

1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM

NEC => Renesas Technology 

µPD16498

3.2 Logic System Pins

Symbol

PSX

Name

Data transfer

selection

/CS1,

CS2

/RD

(E)

Chip select

Read

(enable)

Pad No.

106, 107

112, 113,

114, 115

124, 125

/WR

(R,/W)

Write

(read/write)

122, 123

C86

Interface selection

104, 105

RDS

Data pin selection

127,128

I/O

Input

Input

Input

Input

Input

Input

(1/2)

Description

This pin is used to select between parallel data input and serial

data input.

PSX = H: Parallel data input

PSX = L: Serial data input

These pins are used for chip select signals. When /CS1 = L (CS2

= H), the chip is active and can perform data input/output

operations including command and data I/O.

When i80 series parallel data transfer (/RD) has been selected,

the signal at this pin is used to enable read operations. Data is

output to the data bus only when this pin is L.

When M68 series parallel data transfer (E) has been selected,

the signal at this pin is used to enable write operations. Data is

written at the falling edge of this signal.

When i80 series parallel data transfer (/WR) has been selected,

the signal at this pin is used to enable write operations. Data is

written at the rising edge of this signal.

When 68 series parallel data transfer (R,/W) has been selected,

this pin is used to determine the direction of data transfer.

L: Write

H: Read

This pin is used to switch between interface modes (i80 series

CPU or M68 series CPU).

L: Selects i80 series CPU mode

H: Selects M68 series CPU mode

This pin determines the direction of a data as follows. Fixed to

low level at the time serial data input (PSX = L).

RDS P7 P6 P5 P4 P3 P2 P1 P0

Low D7 D6 D5 D4 D3 D2 D1 D0

High D0 D1 D2 D3 D4 D5 D6 D7

P0 to P5,

Data bus

P6 (SCL)

P7 (SI)

(serial clock)

(serial input)

RS

Index

register/data,

command

selection

/RES

Reset

148 to 145, 143 to 140, I/O

138 to 135,

133, 132,

131, 130

119, 120

Input

117, 118

Input

These pins comprise an 8-bit bidirectional data bus that connects

to an 8-bit or 16-bit standard CPU bus.

When the serial interface has been selected (PSX = L), P6

functions as a serial clock input pin (SCL) and P7 functions as a

serial data input pin (SI). In either case, pins P0 to P5 are in high

impedance mode.

When the chip is not selected, P0 to P7 are in high impedance

mode.

Usually, this pin is connected to the LSB of the standard CPU

address bus and is used to distinguish between data from index

registers and data/commands.

RS = H: Indicates that data from D0 to D7 is data/command

RS = L : Indicates that data from D0 to D7 is index register

contents

When /RES is low, an internal reset is performed. The reset

operation is executed at the /RES signal level.

Data Sheet S15730EJ2V0DS

11

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