UPD16498 Ver la hoja de datos (PDF) - NEC => Renesas Technology
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Fabricante
UPD16498
NEC => Renesas Technology
UPD16498 Datasheet PDF : 95 Pages
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µPD16498
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface
5.1.1 Selection of interface type
The µPD16498 chip transfers data using an 8-bit bidirectional data bus (P7 to P0) or a serial data input (SI). Setting the
polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the
following table.
PSX
CS RS /RD /WR C86 RDS P7
P6
P5
P4
P3
P2
P1
P0
H: Parallel input CS RS /RD /WR C86 L
D7
D6
D5
D4
D3
D2
D1
D0
L: Serial input
H
D7
D6
D5
D4
D3
D2
D1
D0
CS
RS
Note1 Note1 Note1 LNote2 SI
SCL
Hi-ZNote3
Notes 1. Fixed as either High or Low.
2. Fix the RDS pin to Low level when the serial interface has been selected (PSX = L).
3. Hi-Z: High impedance
5.1.2 Parallel interface
When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection
to an i80 series or M68 series CPU (see table below).
C86
/CS1
CS2
RS
/RD
/WR
P7 to P0
H: M68 series CPU
/CS1
CS2
RS
E
R,/W
D7 to D0
L: i80 series CPU
/CS1
CS2
RS
/RD
/WR
D7 to D0
The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the
following table.
Common
RS
1
1
0
0
M68
R,/W
1
0
1
0
i80
/RD
/WR
0
1
1
0
0
1
1
0
Function
Reads display data and registers
Writes display data and registers
Prohibited
Writes to index register
16
Data Sheet S15730EJ2V0DS
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