UPD16498 Ver la hoja de datos (PDF) - NEC => Renesas Technology
Número de pieza
componentes Descripción
Fabricante
UPD16498
NEC => Renesas Technology
UPD16498 Datasheet PDF : 95 Pages
| |||
µPD16498
5.2 Display Data RAM
5.2.1 Display data RAM
This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits (32 x 8 bits) x 128 bits. Any
specified bit can be accessed by selecting the corresponding X address and Y address. The display data D0 to D7 sent
from the CPU correspond to SEGx on the LCD display (see Figure 5-5).
The CPU writes data to and reads data from the display RAM via the I/O buffer, and these read/write operations are
independent of the signal read operations for the LCD driver. Accordingly, there are no adverse effects (such as flicker) in
the LCD display when display data RAM is accessed asynchronously.
Figure 5-5. Display Data RAM
MSB
D7
D6
Pixel 1
D5
D4
Pixel 2
LSB
D3
D2 D1
D0
Pixel 3
Pixel 4
LCD panel
Pixel 1
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 3
Pixel 4
Pixel 4
Pixel 1
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 3
Pixel 4
Pixel 4
X address 00H
X address 01H
D7 D6 D5 D4
0111
1000
0000
0111
1000
Display data
00
00
00
00
00
COM0
COM1
COM2
COM3
COM4
SEG1 SEG2
LCD display
5.2.2 X address circuit
As shown in Figure 5-6, the display data RAM's X address is specified via the X address register (R3). When using X
address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is
incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set
back to 00H.
For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is
incremented after each read or write operation and the X address is set back to 00H.
Data Sheet S15730EJ2V0DS
21
Share Link: