µPD16498
(1) i80 series parallel interface
When i80 series parallel data transfer has been selected, data is written to the µPD16498 at the rising edge of the /WR
signal. The data is output to the data bus when the /RD signal is L.
/CS1
(CS2=H)
Figure 5-1. i80 Series Interface Data Bus Status
/WR
/RD
Hi-Z
DBn
Hi-Z
Valid data
Data write
Data Read
(2) M68 series parallel interface
When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W
signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H, outputs valid
data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the R,/W signal (R,/W = L)
Figure 5-2. M68 Series Interface Data Bus Status
/CS1
(CS2=H)
R,/W
E
Hi-Z
Hi-Z
DBn
Invalid data
Valid data
Data Sheet S15730EJ2V0DS
17