SPT7814(1991) Ver la hoja de datos (PDF) - Signal Processing Technologies

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SPT7814
(Rev.:1991)

AN7810/14 EVALUATION BOARD

Signal Processing Technologies 

14 data sheet (refer to the recommended interface circuit in the

SPT7810 or SPT7814 data sheet). This circuit has an

advantage over the EB7810/14 reference driver circuit as it

will have better control on the full scale error and over

temperature.

POWER SUPPLY CIRCUITS

EB7810/14 also provides the on-board power supplies to

drive the SPT7810/14. Vcc and Vee are generated from the

analog supplies ±15 V respectively. U4 (LM317) is the

positive regulator to drive Vcc with an adjustable range of

typically from +4 V to +6 V with the potentiometer R3. TP3 is

the monitoring test point for U4 regulated output or Vcc.

Similarly, U5 (LM337) is the negative regulator to support

Vee. Its adjustable range is from -4 V to -6 V with the

potentiometer R4. TP4 is the monitoring test point for Vee.

TP3 and TP4 are to be referenced to the AGND test point.

Vecl (-2 V), the outputs ECL pull down load, is also internally

generated using the negative regulator LM337 (U11) from the

digital -5.2 V supply. Its range is from -1.25 V to -3.3 V by

adjusting the potentiometer R5. TP5 is the monitoring point

for the Vecl and should be referenced to the DGND test point

(provided).

Table II - Recommended Operating Voltage Range

Reference Test Point Min Typ Max Adjust

VST U14, PIN20 +1.995 V +2.0 V +2.005 V R1

VSB U14, PIN24 -2.005 V -2.0 V -1.995 V R2

Vcc

TP3

+4.75 V +5.0 V +5.25 V R3

Vee

TP4

- +5.45 V - 5.2 V - 4.95 V R4

Vecl TP5

- 1.90 V - 2.0 V - 2.10 V R5

All three circuits (U4, U5 and U11) were designed to include

a protection circuit against capacitor discharge that could

damage the regulators. Table II shows the recommended

operating voltage range of the SPT7810/14 without affecting

the performance of the device. In addition, it indicates the

corresponding potentiometer if tuning is required.

SPT7810 OR SPT7814, 10-BIT ADC

The SPT7810 integrated circuit is a 10-bit analog-to-digital

converter with an over-range bit, capable of digitizing an input

signal up to 10 MHz with a minimum update rate of 20 mega-

samples per second (MSPS). The SPT7814 has the same

pin-out as in the SPT7810 except that it is twice as fast, 40

MSPS for the sampling frequency. On both devices, the

expected full scale analog input range is from VST to VSB.

The analog input is latched at the leading edge of the CLK.

There are 11 digital ECL outputs. D0-D9 are the parallel ECL

output bits, with D0 the LSB and D9 the MSB. D10 is the over-

range bit. The data outputs are latched at the rising edge of

the CLK, with a propagation delay of typically 4 nsec. There

is one clock latency between CLK and valid output data (see

timing diagram section). RN1 and RN2 are 8-pin 51 Ω SIPs,

used as the ECL digital output loads (to Vecl = -2 V). The

output code is a straight binary:

Table III - SPT7810/14 Output Coding (Ø indicates the

flickering bit between logic 0 and 1)

Analog In

Over-range Bit

< -2.0 V

0

-2.0 V

0

0.0 V

0

+2.0 V

0

≤ +2.0 V + 1 LSB

1

ECL Output Code

OO OOOO OOOO

OO OOOO OOOØ

ØØ ØØØØ ØØØØ

11 1111 111Ø

11 1111 1111

Pins 21 and 22 are the analog inputs. They are internally

connected together serving as Kelvin source and sense.

Selecting the analog input driver for the SPT7810 and

SPT7814 should be less of an issue than in most Flash ADCs

because the input impedance and input capacitance are

typically 300 kΩ and 5 pF, respectively. For example, at 0

MHz and ±2.0 V P-P sinewave input, the input driver source

only requires 628 µA of peak output current. For this reason,

EB7810/14 does not need to include the input driver. The

analog input is directly fed from a BNC (VIN). R10 (51 Ω) is

the analog input source termination, mounted on a socket as

a user-selectable termination.

The SPT7810/14 can be driven from a single-ended ECL

clock input through the CLK, since NCLK is internally biased

to -1.3 V through 6 kΩ. NCLK may be left open, but a 0.01 µFd

bypass capacitor from NCLK to DGND is recommended.

EB7810/14 provides a differential clock circuit driver from a

single-ended clock input (see Clock Driver section).

CLOCK DRIVER

To avoid any confusion, CLK IN is the single-ended input

clock to the EB7810/14 (evaluation board), CLK and NCLK

are the differential input clocks to the SPT7810 or SPT7814,

and CCLK is the capture clock used for the output latches.

The clock driver provides a differential ECL clock to pins 14

and 15 of the SPT7810 or SPT7814 from a single-ended

clock. U1 is the SPT ultra-fast dual comparator, HCMP96870,

with a propagation delay of typically 2 nsec (10 mV of over-

drive or higher). The single-ended clock with 50 Ω of

characteristic output impedance can be applied via the BNC

(CLK IN). It can be either sinusoidal or square wave source

SPT

AN7810/14

3

12/11/91

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