SPT7814(1991) Ver la hoja de datos (PDF) - Signal Processing Technologies
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SPT7814 Datasheet PDF : 13 Pages
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RECONSTRUCTION DAC
U12 is the SPT HDAC52160, high speed 16-bit D/A con-
verter. It is the fastest 16-bit DAC on the market, with a typical
full scale settling time of 150 nsec. The interfacing circuit is
configured in a ±2.5 V bipolar mode of operation. U13 is the
I/V converter, to provide a low impedance output voltage and
improve the accuracy by keeping the HDAC52160 output at
virtual ground. Gain and offset adjustments are provided to
facilitate any possible needs in testing the SPT7810 or
SPT7814. One test requiring these options is the low
frequency linearity error test, as suggested in the Accuracy
Test # 2 section). The BNC (DAC OUT) is the ADC output
reconstruction DAC monitoring signal. This signal is 180° out
of phase with respect to the analog input signal (VIN). The
recommended maximum update rate for the HDAC52160 is
1 MHz. When the CLK IN exceeds 1 MSPS, decimating
CCLK is necessary to meet the HDAC52160 settling. Note
that the glitch energy is significant in the HDAC52160.
EB7810/14 does not include a de-glitcher to minimize the
glitch. The biggest glitch occurs at mid-scale lasting no more
than 50 ns.
Table VIII - HDAC52160 Coding
Digital Input
00 0000 0000
01 1111 1111
11 1111 1111
Theoretical DAC Out
+2.4951 V
0.00 V
-2.5000 V
SPT7810/14 CHARACTERIZATION
The EB7810/14 was designed to provide optimum capability
in fulfilling the above characterization needs.
EQUIPMENT HOOK-UP
Coherent testing is recommended in characterizing the
SPT7810/14. All three signals (VIN, CLK IN and CCLK) are
synchronized. This testing gives well defined results when
using the following suggested techniques for evaluating the
performance of the device. These techniques will also
significantly reduce the testing time, especially the dynamic
testing. The diagram in figure 5 suggests one way to achieve
this goal. Generator #1 is the Analog input. Generator 2 is
the sampling clock (single-ended) with maximum peak-to-
peak voltage of ±2.5 V The signal out from generator # 2 can
be either a square or sinewave, but BPF-2 will not be needed
if a square wave signal is used. Generator 3 is the capture
clock, ECL. A phase adjustment option for generator 3 is
necessary to place the edge of the capture clock at the proper
setup time. These last two generators (Clock In and Capture
Clock) require a 50 Ω characteristic output impedance.
Figure 5 -Synchronous Set-Up
REF OUT
OUT
GENERATOR # 1
REF IN
OUT
GENERATOR # 2
REF IN
OUT
GENERATOR # 3
BPF-1
BPF-2
ANALOG INPUT
ANALOG INPUT
CAPTURE CLOCK
The performance at speed is the main goal in evaluating any
ADC, but it is beneficial to start from a relatively low speed and
verify key parameters. It is also beneficial to at least predict
performance at speed. If the transition noise and/or the
differential linearity of the device perform poorly at low
frequency, then the SNR at speed cannot be expected to be
better. In addition, the low frequency set-up can be useful as
a verification tool for the test set-up.
At low frequency there are many ways of characterizing the
differential linearity error (DLE), integral linearity error (ILE),
transition noise, missing codes, synchronous noise, non-
monotonicity, power supply sensitivity and power supply
currents. SPT will guide the user through two classical yet
powerful testing approaches to achieve fast and relatively
accurate results.
High frequency or dynamic testing, the missing codes test,
ILE, DLE, VOS and gain error tests are based on statistical
results. They can be performed using the Histogram tech-
nique. SNR and THD are tested by using the Fast Fourier
Transform (FFT). These dynamic tests are explained in SPT
application notes AN100 or AN101. Many additional articles
are also available for this application.
SELECTION OF THE SIGNAL GENERATORS
For very high speed and high accuracy ADC testing, selection
of both analog and clock inputs is critical. Two parameters
are important in selecting generators #1 and #2:
1) The purity of the output sinewave must be at least 72
dB of SNR (12 bit). An appropriate band pass filter
(BPF-1) installed after the generator will help improve
the SNR.
2) The sampling clock jitter or aperture jitter. This jitter
can originate both inside and outside the A/D con-
verter.
Consider the selection of an acceptable clock generator. The
uncertainty of the clock placement due to the time jitter
(aperture jitter) will degrade the effective performance of the
device. This jitter is translated into the ADC amplitude error
and is proportional to the analog input slew rate. For a
sinusoidal input, the uncertainty of the clock edge placement
from cycle to cycle due to the equipment jitter will have an
effect on the A/D converter performance, especially the SNR.
SPT
AN7810/14
6
12/11/91
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