SPT7814(1991) Ver la hoja de datos (PDF) - Signal Processing Technologies
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SPT7814 Datasheet PDF : 13 Pages
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SNR (Max) = {20 LOG [1/ ( 2π Fin Tj )] + 3.02 } dxB,
:
Fin = analog input frequency
and
Tj = the aperture jitter in RMS
Where
Based on SPT’s observation, it is easier to find a low aperture
jitter in a synthesizer than in a pulse generator. For this
reason, EB7810/14 uses for the differential driving circuit to
the SPT7810/14 a single-ended signal source where a
sinewave can be used. In the first evaluation of the SPT7810/
14, equipment used was a HP8644A (or HP3325A at low
frequency where a ramp signal source was needed), FLUKE
6060B, and HP3325A for the generator #1, #2 and #3,
respectively.
ACCURACY TEST 1
This section is intended to suggest one approach to visual
evaluation of the differential linearity error (DLE), missing
codes (MC), non-monotonicity, synchronous noise and tran-
sition noise. The BNC DAC OUT can be the monitoring point
to view the quality of the quantization signal, but this may
pose a great deal of difficulty. SPT suggests another ap-
proach commonly used in the industry. This approach is to
use a three bit reconstruction DAC generated from the last
three LSB’s TTL outputs. This circuit is shown in figure 6.
Figure 6 - Three-Bit Reconstruction DAC Circuit
(All Resistors Are 5%)
B2
5K
B1
10K
20K
B0
10K
DGND
TO SCOPE
B0, B1, B2 and DGND are available within EB7810/14 as a
single pin socket. Physically, they are located between U12
(HDAC52160) and the connector P2. Use a function genera-
tor for the generator #1 (HP3325A or equivalent) and set-up
for a ramp output. Replace the BF-1 by an RC low pass filter
to eliminate all high frequency components. The slew rate of
this ramp signal should be set to 1 LSB per n conversions
(sampling period) for a desired (1/n) test resolution. A
minimum of n = 10 is recommended for this application. The
P-P voltage and the period of the ramp input are then
dependent on the selection of the number of steps (LSBs)
within one ramp’s period. Note that R10 (51 Ω) may need to
be removed. The CLK IN and CCLK are to be set to the same
relatively low frequency, less than 1 MHz. Adjustments are
needed to meet the tpwH and ts specifications ( see figure 4
and table VII).
The following formulas summarize the criteria for selecting
the analog ramp input signal:
The ramp peak-to-peak voltage: V(p-p)=m ( FSR / 1024)
The ramp period : T=(m) ( n) / Fs
Where:
m= desired number of steps (LSBs) per ramp’s period
Fs=sampling frequency
FSR=full scale range (typically SPT7810’s FSR is 4.8V)
n=desired test resolution or the number of conversions / LSB
Figure 7 shows the relationship between the analog input
ramp signal and the resulting three-bit reconstruction DAC. It
shows 16 LSBs of P-P input voltage (i.e., two 8-level steps)
per period. For an ideal ADC and an ideal ramp input, its
digital output code will change state by 1 LSB every (n)th
conversion (dash line in the transfer curve). Any error in the
ADC will make the corresponding output codes change their
state before or after the (n)th conversion. This error will
translate into the smaller or larger of the respective step
width. The DLE will be judged visually by comparing the
actual step size with respect to the ideal step with ±(1/n) LSB
of accuracy. In this case, the ideal step is the average of the
step size. Other errors (MC, transition noise and non-
monotonicity) can be resolved in a similar way. Figure 7
gives the identification of each error from the actual transfer
curve.
Example:
1) SPT7810 is operated at 500 kHz (sampling frequency).
2) (1/10) of the test resolution is desired.
3) The scope is externally triggered to the ramp input. Three
retraces of 8-level steps (or 24 total
steps) per
ramp’s period are selected .
What peak-to-peak voltage (Vp-p) and period (T) of the
ramp input signal are required to drive the SPT7810 ?
Answer:
1) Fs = 500 kHz,
2) n = 10 ,
3) m = 24,
then V(p-p) = m ( FSR / 1024) = 24( 4 /1024) = 94 mV
and T = (m) ( n) / Fs = (24) (10) / 5000,000 = 480 µsec
Note the above input signal will only cover 24 parts in 1024 of
the FSR. To identify all errors through the full scale range,
sweep the ramp input slowly from -FS to +FS and observe the
output steps for the MC, transition noise, DLE and non-
monotonicity as indicated in the transfer curve (Figure 7 ).
SPT
AN7810/14
7
12/11/91
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