SPT7814(1991) Ver la hoja de datos (PDF) - Signal Processing Technologies

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SPT7814
(Rev.:1991)

AN7810/14 EVALUATION BOARD

Signal Processing Technologies 

with the peak-to-peak voltage not to exceed ±2.5 V. This ±2.5

V limitation is due to the input common mode range limitation

of U1. The output of U1 is a differential ECL clock that will

feed into the CLK and CLK of SPT7810 or SPT7814. CLK

(SPT7810/14, pin 14) and CLK IN are in phase.

When operating the SPT7810 or SPT7814 above 3 MSPS,

set the SW1 to HS position (upper position) . The clock input

to the SPT7810/14 (CLK) should be adjusted to obtain

roughly a 50% duty cycle by tuning potentiometer R20.

Below 3 MSPS, set the SW1 to LS position (lower position).

The clock (pin 14) positive pulse width (tpwH) must be kept

at 300 nsec maximum, due to the SPT7810/14’s internal track

and hold amplifier requirement (see timing diagram). The

potentiometer R21 is adjusted to inject the appropriate

hysterisis to U1 when operating at a relatively low frequency

sinewave (less than 3 MSPS). This eliminates any unstable

transitions due to low input slew rate.

Table IV: SPT7810 /14 Clock Driver Set-up

Sampling

Frequency

Below 3 MSPS

3 MSPS & above

SW1 Position

LS (lower position)

HS (upper position)

CLK Pulse

Width (tpwH)

300 nsec Max

50% duty cycle

PJ1 and PJ2 are the probe jack monitoring points forCLK

and CLK, respectively. Use these scope monitoring points

when adjusting the clock pulse width, tpwH. They are

installed to minimize the ringing and over-shoot of both

signals due to the long ground probe of the scope.

ECL OUTPUT DATA LATCHES

U6 and U7 (10H176) are the output latches. The BNC

connector (CCLK) is the capture clock, which has a 51 Ω

termination (R11) on board. The output of the data latches

(D0-D10) are routed through the standard 26-pin female

ribbon connector (P1). Provisions have been made to

minimize the reflection due to a long routing from P1 to

another system. RN3 and RN4 are 8-pin SIP, 7-680 Ω ECL

pull down resistors (to -5.2 V), mounted on an 8-pin strip

socket. If a long cable is needed to interface between

EB7810/14 and another system, substitute RN3 and RN4

with the appropriate load terminating resistors to minimize

the ringing or overshoot of the signal. If the over-range bit

D10 is not needed, remove jumper J2 from the board, then

add a jumper from U6, pin 7 to Vecl.

Table V - P1, 26- Pin Female Ribbon Connector

P1

Function

Logic

1

CCLK

2

DGND

3

D0 (LSB)

EC

DGND

ECL

4

DGND

5

D1

6

DGND

7

D2

8

DGND

DGND

ECL

DGND

ECL

DGND

9

D3

10

DGND

11

D4

12

DGND

ECL

DGND

ECL

DGND

13

D5

ECL

14

DGND

15

D6

16

DGND

DGND

ECL

DGND

17

D7

18

DGND

ECL

DGND

19

D8

20

DGND

ECL

DGND

21

D9 (MSB)

22

DGND

23

N/C

ECL

DGND

ECL/LOW

24

DGND

DGND

25

D10 (Over-range)

ECL*

26

DGND

DGND

* IF J2 jumper is removed, then P1 pin 25 is at logic low when

a jumper from U6, pin 7 to Vecl is added.

Table VI - P2, 26-pin Female Ribbon Connector

ECL-To-TTL Translators

P2

Function

Logic

1

CCLK-NOT*

TTL

2

DGND

DGND

3

D0 (LSB)

TTL

4

DGND

DGND

5

D1

TTL

6

DGND

DGND

7

D2

TTL

8

DGND

DGND

9

D3

TTL

10

DGND

DGND

11

D4

TTL

12

DGND

DGND

13

D5

TTL

14

DGND

DGND

15

D6

TTL

16

DGND

DGND

17

D7

18

DGND

19

D8

20

DGND

21

D9 (MSB)

TTL

DGND

TTL

DGND

TTL

22

DGND

DGND

23

N/C

TTL/LOW

24

DGND

DGND

25

D10 (Over-range)

TTL**

26

DGND

DGND

* When J4 and J5 jumpers are installed, the TTL/CCLK will be

inverted. If a non-inverted TTL / CCLK with respect to the ECL/

CCLK is required, then install J3 and J6 in place of J4 and J5.

** If J2 jumper is removed, pin 25 of P1 is at logic low (add jumper

from U6, pin 7 to Vecl).

SPT

AN7810/14

4

12/11/91

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