GT28F400B3B150 Ver la hoja de datos (PDF) - Intel
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GT28F400B3B150 Datasheet PDF : 49 Pages
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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
E
After any program or block erase operation is
complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
Refer to AP-617 Additional Flash Data Protection
Using VPP, RP#, and WP# for a circuit-level
description of how to implement the protection
schemes discussed in Section 3.5.
3.7 Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling. System
designers should consider three supply current
issues:
1. Standby current levels (ICCS)
2. Active current levels (ICCR)
3. Transient peaks produced by falling and rising
edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
3.7.1
VPP TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the VPP power
supply trace by the printed circuit board designer.
The VPP pin supplies the flash memory cells current
for programming and erasing. VPP trace widths and
layout should be similar to that of VCC. Adequate
VPP supply traces, and decoupling capacitors
placed adjacent to the component, will decrease
spikes and overshoots.
28
PRELIMINARY
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