GT28F400B3B150 Ver la hoja de datos (PDF) - Intel
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GT28F400B3B150 Datasheet PDF : 49 Pages
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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
E
3.3 Block Locking
The Smart 3 Advanced Boot Block flash memory
architecture features two hardware-lockable
parameter blocks so that the kernel code for the
system can be kept secure while other parameter
blocks are programmed or erased as necessary.
3.3.1
VPP = VIL FOR COMPLETE
PROTECTION
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device. When VPP is below VPPLK, any program or
erase operation will result in a error, prompting the
corresponding Status Register bit (SR.3) to be set.
3.3.2
WP# = VIL FOR BLOCK LOCKING
The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
parameter blocks (blocks #37 and #38 for the
16-Mbit, blocks #21 and #22 for the 8-Mbit, and
blocks #13 and #14 for the 4-Mbit) are lockable. For
the bottom configuration, the bottom two parameter
blocks (blocks #0 and #1 for 4-/8-/16-Mbit) are
lockable. Unlocked blocks can be programmed or
erased normally (unless VPP is below VPPLK).
3.3.3
WP# = VIH FOR BLOCK UNLOCKING
WP# = VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in
previous Boot Block devices. WP# controls all block
locking and VPP provides protection against
spurious writes. Table 8 defines the write protection
methods.
3.4 VPP Program and Erase
Voltages
Intel’s Smart 3 products provide in-system
programming and erase at 2.7V–3.6V VPP. For
customers requiring fast programming in their
manufacturing environment, Smart 3 includes an
additional low-cost, backward-compatible 12V
programming feature.
26
The 12V VPP mode enhances programming
performance during the short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12V may be applied
to VPP during program and erase operations for a
maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. VPP may be
connected to 12V for a total of 80 hours maximum.
Stressing the device beyond these limits may cause
permanent damage.
Table 8. Write Protection Truth Table for
Advanced Boot Block Flash Memory Family
VPP WP# RP#
Write Protection
Provided
X
X
VIL
VIL
X
VIH
≥ VPPLK VIL
VIH
All Blocks Locked
All Blocks Locked
Lockable Blocks
Locked
≥ VPPLK VIH
VIH
All Blocks Unlocked
3.5 Power Consumption
While in operation, the flash device consumes
active power. However, Intel Flash devices have a
three-tiered approach to power savings that can
significantly reduce overall system power
consumption. The Automatic Power Savings (APS)
feature reduces power consumption when the
device is idle. If the CE# is deasserted, the flash
enters its standby mode, where current
consumption is even lower. If RP# = VIL the flash
enters a deep power-down mode, where current is
at a minimum. The combination of these features
can minimize overall memory power consumption,
and therefore, overall system power consumption.
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a logic-
high level, the device is in the active mode. Refer to
the DC Characteristics tables for ICC current values.
Active power is the largest contributor to overall
system power consumption. Minimizing the active
current could have a profound effect on system
power consumption, especially for battery-operated
devices.
PRELIMINARY
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