SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

Número de pieza

componentes Descripción

Fabricante

SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Register

Name

SR5B0

SR5B1

SR5B2

SR5B3

SR5B4

SR5B5

SR5B6

SR5B7

ADR 5 Data Link Bit for Internal Use

Bit

Description

0

First bit of service word of frame 15.

1

First bit of service word of frame 13.

These bits (0 and 1) are updated at the beginning of every

received multiframe.

If CRC4-mode is not enabled, these are set to “0”.

2

First bit in FAS-word, used only in double Frame format

(otherwise fixed at "1").

3

Transmit Parity Error

If channel parity check is enabled, this bit is set after a channel

parity error occurs.

It is also set during alarm simulation.

4

Global Parity Error

Set by a parity error in any transmitted or received channel.

Also set during alarm simulation.

5

DMA Request Slip

If the use of the TS16 signalling stacks is enabled, this bit is set

if required access is not completed before the signalling stack

gets updated.

6

Receive Sn-bit Stack Flag

Will be set at the beginning of every received CRC4 multiframe.

It will be reset after a read access to the Receive S -bit

n

stack occurs or at the beginning of frame 15 in the multiframe.

A read access should occur only if this flag is set to “1”. Should

be monitored at time intervals of less than 2ms.

7

Transmit Sn-bit Stack Flag

Will be set at the beginning of every transmitted CRC4

multiframe.

It will be reset after a write access to the Transmit Sn-bit stack

or at the beginning of frame 15 in the multiframe.

A write access should occur to the stack only if this flag is set.

Should be monitored at time intervals of less than 2ms.

30/40

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