SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

ADR 1 Extended Mode Register 1

Register Bit

Name

CX1B0

0

CX1B1

1

CX1B2

2

CX1B3

3

CX1B4

4

CX1B5

5

CX1B6

6

CX1B7

7

Description

Enable Double Frame marker

0: Normal

1: Marker enabled and

provided at CHPAR

pin.

Not used

Fully Bauded data format

0: Half bauded

1: Fully bauded

Extended Code Violation Counter mode

Si-bit zero counter enable

Receive Transparent Mode

Time slot 0 Extended Signalling Transparent Mode. If set, in

Double frame and CRC Multiframe formats only the S bits are

n

transmitted as applied at DXI

Not used

ADR 6 - 9 Idle Channel Register Bank

CX6

IC0 IC1 IC2 IC3 IC4 IC5 IC6 IC7

CX7

IC8

IC15

CX8

IC16

IC23

CX9

IC24

IC31

Note:

0: Normal operation, 1: Idle Channel mode

Timeslot 0 information is overwritten by idle channel code according to the

transparency mode selected.

If Timeslot 16 Signalling stack is enabled and Timeslot 16 is selected for Idle

Channel Code, the idle channel selection will be ignored. The stack has higher

priority.

sames

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