SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

Número de pieza

componentes Descripción

Fabricante

SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Status Register

Register

Name

SR0B0

than

internal

SR0B1

SR0B2

SR0B3

SR0B4

SR0B5

SR0B6

SR0B7

ADR 0 PCM/SA9101 Alarm status

Bit

Description

0

Slip Direction Indication

0 = negative slip, receive route clock frequency higher

internal system clock.

1 = positive slip, receive route clock frequency below

system clock.

1

CRC4 Multiframe alarm

Set after reset, multiframe synchronization lost or via uP-

Interface with command “Force Re-synchronisation”.

Will be reset after receiving 2 multi-frames without errors.

2

Receive Channel Parity Error

Set after device detects a channel parity error.

Cleared by setting control register ADR 0, bit 2 (Clear Channel

Parity Alarm Latch).

3

Receive Slip Indication

This bit changes state when a frame is dropped (RCLK > SCLK)

or repeated (SCLK > RCLK) .

A successful alarm-simulation causes one change.

4

Receive Remote Alarm

Bit 3 of received service word.

5

Loss Of Synchronisation

Will be set if incorrect frame alignment signal or service word

was detected 3 times in sequence.

Is automatically reset after sequence FAS-SW-FAS is received.

Loss of synchronisation is also indicated if “No Signal” occurs

because of no Route Clock.

Alarm Indication Signal (AIS)

If less than two “0’s” are detected in an incoming bitstream of

512 bits, this bit is set to “1”.

7

No Signal

If less than four “1’s” are in a stream of 512 bits or no complete

receive clock pulse occurs within 4 periods of the system clock,

this bit is set to “1”.

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