SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

Número de pieza

componentes Descripción

Fabricante

SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Register

Name

CRBB[0-7]

ADR B Transmit S -bit stack

n

Bit

Description

0-7 5-byte Sn-bit stack, which data will be inserted if CRC and

stack mode enabled and no timeslot 0 transparent mode is

enabled. The Sn-bit information can be written into the

transmit Sn-bit stack when Transmit Sn-bit flag is set (SR5B7).

ADR C Alarm Interrupt Mask Register

Register

Name

CRCB0

Bit

Description

0 Code violation counter saturation

CRCB1

1 Frame error counter saturation

CRCB2

2 CRC error counter saturation

CRCB3

CRCB4

3 Receive slip indication

4

Receive remote alarm

CRCB5

5 No signal

CRCB6

CRCB7

6 Alarm Indication Signal

7

Loss of synchronisation

Note: The alarm source is enabled by setting the corresponding bit to “1”.

Register

Name

CRDB[0-7]

ADR D IDLE Channel code

Bit

Description

0-7 Idle Channel code

During Loop-back, this code is sent to the remote end for the

assigned channel. The specified pattern is also written into all

channels selected via the Idle channel Register Bank, overwriting

whatever information was in those timeslots.

ADR E - F

Not used.

26/40

sames

Share Link: