SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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componentes Descripción

Fabricante

SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Register

Name

CR3B[0-4]

CR3B5

CR3B6

CR3B7

ADR 3 Channel Loop Back

Bit

Description

0-4 The addressed timeslot (1..31) is looped back to the system

interface.

Idle channel code content of control register D for this channel

is sent to remote end.

Code “00000” deactivates loop-back.

5

A “1” disables loop back of selected channel

6

Select single frame delay mode

Signal delay set to max. one frame length., if this bit is at “1”.

7

Alarm Interrupt Acknowledge

A “1” clears AINT. Resetting is not necessary.

Register

Name

CR4B[0-4]

CR4B5

CR4B6

CR4B7

ADR 4 Service Word

Bit

Description

0-4 Y (Sn) bits for national use

These bits are inserted in the service word, if Sn-bit stack mode

is disabled and no TS0 transparent mode is enabled.

5

Send Remote Alarm to Remote End

A “1” causes bit 3 of service word to be set to “1”.

It is ignored if TS0 transparent mode is enabled.

6

Synchronization bit, internally set to “1”. It cannot be overwritten.

7

First bit of service word if double-frame format enabled,

and Non-transparent or Extended TS0 Signalling Transparent

modes enabled.

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