DS80C400 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS80C400

Network Microcontroller

Dallas Semiconductor -> Maxim Integrated 

DS80C400

PIN

NAME

FUNCTION

10

RXClk Receive Clock, Input. The receive clock is a continuous clock sourced from the Ethernet PHY

controller. It is used to provide timing reference for transferring of RX_DV, RX_ER, and

RXD[3:0] signals from the external Ethernet PHY controller to the MAC. The input clock

frequency of RXClk should be 25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation.

For ENDEC operation, RXClk serves the same function, but the input clock frequency should be

10MHz.

11

RX_DV Receive Data Valid, Input. The receive data valid is an active-high input from the external

Ethernet PHY controller and is synchronous with respect to the RXClk signal. RX_DV is used to

indicate valid nibbles of data for reception on the MII pins RXD.3–RXD.0. RX_DV is asserted

continuously from the first nibble of the frame through the final nibble. RX_DV negates prior to

the first RXClk following the final nibble. RX_DV serves the same function for ENDEC

operation.

9

RX_ER Receive Error, Input. The receive error is an active-high input from the external Ethernet PHY

controller and is synchronous with respect to the RXClk signal. RX_ER is used to indicate to the

MAC that an error (e.g., a coding error, or any error detectable by the PHY) was detected

somewhere in the frame presently being transmitted by the PHY. RX_ER has no effect on the

MAC while RX_DV is deasserted. RX_ER should be low for ENDEC operation.

17

RXD.3 Receive Data, Input. The receive data inputs provide 4-bit nibbles of data for reception over the

16

15

14

RXD.2

RXD.1

RXD.0

MII. The receive data is synchronous with respect to the RXClk signal. For each RXClk period

when RX_DV is asserted, RXD.3–RXD.0 have the data to be received by the MAC. When

RX_DV is deasserted, the RXD data should be ignored. For ENDEC operation, only RXD.0 is

used for reception of frames.

1

CRS Carrier Sense, Input. The carrier sense signal is an active-high input and should be asserted by the

external Ethernet PHY controller when either the transmit or receive medium is not idle. CRS

should be deasserted by the PHY when the transmit and receive mediums are idle. The PHY

should ensure that the CRS signal remains asserted throughout the duration of a collision

condition. The transitions on the CRS signal need not be synchronous to TXClk or RXClk. CRS

serves the same function for ENDEC operation.

2

COL Collision Detect, Input. The collision detect signal is an active-high input and should be asserted

by the external Ethernet PHY controller upon detection of a collision on the medium. The PHY

should ensure that COL remains asserted while the collision condition persists. The transitions on

the COL signal need not be synchronous to TXClk or RXClk. The COL signal is ignored by the

MAC when operating in full-duplex mode. COL serves the same function for ENDEC operation.

18

MDC MII Management Clock, Output. The MII management clock is generated by the MAC for use by

the external Ethernet PHY controller as a timing referenced for transferring information on the

MDIO pin. MDC is a periodic signal that has no maximum high or low times. The minimum high

and low times are 160ns each. The minimum period for MDC is 400ns independent of the period

of TXClk and RXClk.

19

MDIO MII Management Input/Output, I/O. The MII management I/O is the data pin for serial

communication with the external Ethernet PHY controller. In a read cycle, data is driven by the

PHY to the MAC synchronously with respect to the MDC clock. In a write cycle, data from the

MAC is output to the external PHY synchronously with respect to the MDC clock.

99

OW 1-Wire Data, I/O. The 1-Wire data pin is an open-drain, bidirectional data bus for the 1-Wire Bus

Master. External 1-Wire slave devices are connected to this pin. This pin must be pulled high by

an external resistor, normally 2.2kŸ.

100

OWSTP

Strong Pullup Enable, Output. This 1-Wire pin is an open-drain active-low output used to enable

an external strong pullup for the 1-Wire bus. This pin must be pulled high by an external resistor,

normally 10kŸ. This functionality helps recovery times when the 1-Wire bus is operated in

overdrive and long-line standard communication modes. It can optionally be enabled while the bus

master is in the idle state for slave devices requiring sustained high-current operation.

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