DS80C400 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS80C400 Datasheet PDF : 10 Pages
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DS80C400
DETAILED DESCRIPTION
The DS80C400 is a fast 8051-compatible microcontroller that executes instructions up to three times
faster than an original 8051 at the same crystal speed. Its maximum system-clock frequency of 75MHz
results in a minimum instruction cycle time of 54ns. Access to large program or data memory areas is
simplified with a 24-bit addressing scheme that supports up to 16MB of flat memory. To accelerate data
transfers between the microcontroller and the 16MB memory map, the DS80C400 provides four data
pointers, each of which can be configured to automatically increment or decrement upon execution of
certain data pointer-related instructions. The mircocontroller’s hardware math accelerator further
increases the speed of 32-bit and 16-bit multiply and divide operations as well as high-speed shift,
normalization, and accumulate functions.
With extensive networking and I/O capabilities, the DS80C400 is equipped to serve as a central controller
in a multitiered network. The 10/100 Ethernet media access controller (MAC) enables the DS80C400 to
access and communicate over the Internet. While maintaining a presence on the Internet, the
microcontroller can actively control lower tier networks with dedicated on-chip hardware. These
hardware resources include a full CAN 2.0B controller, a 1-Wire net controller, three full-duplex serial
ports, and eight 8-bit ports (up to 64 digital I/O pins).
Instant connectivity and networking support are provided through an embedded 64kB ROM. This ROM
contains firmware to perform a network boot over an Ethernet connection using DHCP in conjunction
with TFTP. The ROM firmware realizes a full, application-accessible TCP/IP stack, supporting both IPv4
and IPv6, and implements UDP, TCP, DHCP, ICMP, and IGMP. In addition, a priority-based,
preemptive task scheduler is also included. The firmware has been structured so that a MAC address can
optionally be acquired from an IEEE-registered DS2502-E48.
The 10/100 Ethernet MAC featured on the DS80C400 complies with both the IEEE 802.3 MII and
ENDEC PHY interface standards. The MII interface supports 10/100Mbps bus operation, while the
ENDEC interface supports 10Mbps operation. The MAC has been designed for low-power standard
operation and can optionally be placed into an ultra-low-power sleep mode, to be awakened manually or
by detection of a Magic Packet or wake-up frame. Incorporating a buffer control unit reduces the burden
of Ethernet traffic on the CPU. This unit, after initial configuration through an SFR interface, manages all
Tx/Rx packet activity and status reporting through an on-chip 8kB SRAM. To further reduce host
(DS80C400) software intervention, the MAC can be set up to generate a hardware interrupt following
each transmit or receive status report. The DS80C400 MAC can be operated in half-duplex or full-duplex
mode with flow control, and provides multicast/broadcast-address filtering modes as well as VLAN tag-
recognition capability.
The DS80C400 features a full-function CAN 2.0B controller. This controller provides 15 total message
centers, 14 of which can be configured as either transmit or receive buffers and one that can serve as a
receive double buffer. The device supports standard 11-bit or 29-extended message identifiers, and offers
two separate 8-bit media masks and media arbitration fields to support the use of higher-level CAN
protocols such as DeviceNet and SDS. A special auto-baud mode allows the CAN controller to quickly
determine required bus timing when inserted into a new network. A SIESTA sleep mode has been made
available for times when the CAN controller can be placed into a power-saving mode.
The DS80C400 has resources that far exceed those normally provided on a standard 8-bit microcontroller.
Many functions, which might exist as peripheral circuits to a microcontroller, have been integrated into
the DS80C400. Some of the integrated functions of the DS80C400 include 16 interrupt sources (six
external), four timer/counters, a programmable watchdog timer, a programmable IrDA output clock, an
oscillator-fail detection circuit, and an internal 2X/4X clock multiplier. This frequency multiplier allows
the microcontroller to operate at full speed with a reduced crystal frequency, reducing EMI.
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