DS80C400 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS80C400

Network Microcontroller

Dallas Semiconductor -> Maxim Integrated 

DS80C400

PIN

NAME

FUNCTION

P6.0–P6.7

Port 6, I/O. Port 6 can function as an 8-bit, bidirectional I/O port, as program and data memory

address/chip-enable signals, and/or a third serial port. The reset condition of Port 6 is all bits at

logic 1 through a weak pullup. The logic 1 state also serves as an input mode, since external

circuits writing to the port can overdrive the weak pullup. When software clears any port pin to 0,

the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a

reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver, followed

by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again

becomes the output (and input) high state.

Port Alternate Function

56

P6.0 CE4 Program Memory Chip Enable 4

55

P6.1 CE5 Program Memory Chip Enable 5

54

P6.2 CE6 Program Memory Chip Enable 6

53

P6.3 CE7 Program Memory Chip Enable 7

52

P6.4 A20 Program/Data Memory Address 20

51

P6.5 A21 Program/Data Memory Address 21

50

P6.6 RXD2 Serial Port 2 Receive

49

P6.7 TXD2 Serial Port 2 Transmit

Port 7, I/O. Port 7 can function as either an 8-bit, bidirectional I/O port or the nonmultiplexed A0–

A7 signals (when the MUX pin = 1). The reset condition of Port 7 is all bits at logic 1 through a

weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the

port can overdrive the weak pullup. When software clears any port pin to 0, a strong pulldown is

activated that remains on until either a 1 is written to the port pin or a reset occurs. Writing a 1

after the port has been at 0 activates a strong transition driver, followed by a weaker sustaining

pullup. Once the momentary strong driver turns off, the port once again becomes the output (and

input) high state.

Port Alternate Function

78

A0

P7.0 A0 Program/Data Memory Address 0

77

A1

P7.1 A1 Program/Data Memory Address 1

76

A2

P7.2 A2 Program/Data Memory Address 2

75

A3

P7.3 A3 Program/Data Memory Address 3

74

A4

P7.4 A4 Program/Data Memory Address 4

73

A5

P7.5 A5 Program/Data Memory Address 5

72

A6

P7.6 A6 Program/Data Memory Address 6

71

A7

P7.7 A7 Program/Data Memory Address 7

8

TXClk Transmit Clock, Input. The transmit clock is a continuous clock sourced from the Ethernet PHY

controller. It is used to provide timing reference for transferring of TX_EN and TXD[3:0] signals

from the MAC to the external Ethernet PHY controller. The input clock frequency of TXClk

should be 25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. For ENDEC

operation, TXClk serves the same function, but the input clock frequency should be 10MHz.

7

TX_EN Transmit Enable, Output. The transmit enable is an active-high output and is synchronous with

respect to the TXClk signal. TX_EN is used to indicate valid nibbles of data for transmission on

the MII pins TXD.3–TXD.0. TX_EN is asserted with the first nibble of the preamble and remains

asserted while all nibbles to be transmitted are presented on the TXD.3–TXD.0 pins. TX_EN

negates prior to the first TXClk following the final nibble of the frame. TX_EN serves the same

function for ENDEC operation.

3

TXD.3 Transmit Data, Output. The transmit data outputs provide 4-bit nibbles of data for transmission

4

TXD.2 over the MII. The transmit data is synchronous with respect to the TXClk signal. For each TXClk

5

TXD.1 period when TX_EN is asserted,

6

TXD.0 TXD.3–TXD.0 provides the data for transmission to the Ethernet PHY controller. When TX_EN is

deasserted, the TXD data should be ignored. For ENDEC operation, only TXD.0 is used for

transmission of frames.

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