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DS80C400 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

Número de pieza
componentes Descripción
Fabricante
DS80C400
Dallas
Dallas Semiconductor -> Maxim Integrated Dallas
DS80C400 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
FEATURES (continued)
§ 10/100 Ethernet MAC
- Flexible IEEE 802.3 MII (10/100Mbps) and
ENDEC (10Mbps) interfaces allow selection
of PHY
- Low-power operation
- Ultra-low-power sleep mode with Magic
Packetand wake-up frame detection
- 8kB on-chip Tx/Rx packet data memory
with buffer control unit reduces load on
CPU
- Half- or full-duplex operation with flow
control
- Multicast/broadcast address filtering with
VLAN support
§ Full-Function CAN 2.0B Controller
- 15 message centers
- Supports standard (11-bit) and extended
(29-bit) identifiers and global masks
- Media byte filtering to support
DeviceNet, SDS, and higher layer CAN
protocols
- Auto-baud mode and SIESTA low-power
mode
§ Integrated Primary System Logic
- 16 total interrupt sources with 6 external
- Four 16-bit timer/counters
- 2X/4X clock multiplier reduces
electromagnetic interference (EMI)
- Programmable watchdog timer
- Oscillator-fail detection
- Programmable IrDA clock
DS80C400
§ Advanced Power Management
- Energy saving 1.8V Core
- 3.3V I/O operation, 5V tolerant
- Power-management, idle, and stop mode
operations with switchback feature
- Ethernet and CAN shutdown control for
power conservation
- Early warning power-fail interrupt
- Power-fail reset
§ Enhanced Memory Architecture
- Selectable 8/10-bit stack pointer for high-
level language support
- 1kB additional on-chip SRAM usable as
stack/data memory
- 16-bit/24-bit paged/24-bit contiguous
modes
- Selectable multiplexed/nonmultiplexed
external memory interface
- Merged program/data memory space
allows in-system programming
- Defaults to true 8051 memory
compatibility
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