MCC141537 Ver la hoja de datos (PDF) - Motorola => Freescale

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MCC141537

LCD Segment / Common Driver with Controller

Motorola => Freescale 

OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER

Description of Block Diagram Module

Command Decoder and Command Interface

This module determines whether the input data is interpreted as

data or command.

Data is directed to this module based upon the operating mode of

the part and the status of the D/C line. If D/C High, data is written to

Graphic Display Data RAM (GDDRAM). D/C Low indicates that the

data is interpreted as a Command.

Reset has the same function as Power ON Reset (POR). Once

RES received the POR pulse, all internal circuitry will reset to its ini-

tial status. Refer to Command description section for more informa-

tion.

MPU Parallel Interface

The parallel interface consists of 8 bi-directional data lines (D0-D7)

plus R/W and CS. The R/W line High indicates a read of the Graphic

Display Data RAM (GDDRAM). R/W line Low indicates a write to

Display Data RAM or Internal Command Registers depending on the

status of D/C line. The CS line serves as data latch signal (clock).

Refer to AC operation conditions and characteristics section for Par-

allel Interface Timing Description.

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM that holds the bit pat-

tern to be displayed at graphic display mode. The size of the RAM is

determined by number of row times the number of column drivers

(120x16 = 1920 bits). Figure 4 is a description of GDDRAM address

map. For mechanical feasibility, re-mapping on both Segment and

Common outputs are provided.

Row0

Page 1

Page 2

Row15

LSB

MSB

LSB

Com0

(com15)

MSB

Com15

(com0)

Note : The configuration in parentheses represent the remapping of Commons and Columns

Figure 4. Graphic Display Data RAM Address MAP

MC141537

3-108

MOTOROLA

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