SC414 Ver la hoja de datos (PDF) - Semtech Corporation

Número de pieza

componentes Descripción

Fabricante

SC414

6A Integrated FET Regulator with 5V LDO

Semtech Corporation 

SC414/SC424

Applications Information (continued)

LDO Switch-Over Operation

The SC414/SC424 includes a switch-over function for the

LDO. The switch-over function is designed to increase

efficiency by using the more efficient DC-DC converter to

power the LDO output, avoiding the less efficient LDO

regulator when possible. The switch-over function con-

nects the VLDO pin directly to the VOUT pin using an

internal switch. When the switch-over is complete the

LDO is turned off, which results in a power savings and

maximizes efficiency. If the LDO output is used to bias the

SC414/SC424, then after switch-over the device is self-

powered from the switching regulator with the LDO

turned off.

The switch-over logic waits for 32 switching cycles before

it starts the switch-over. There are two methods that

determine the switch-over of V to V .

LDO

OUT

In the first method, the LDO is already in regulation and

the DC-DC converter is later enabled. As soon as the

PGOOD output goes high, the 32 cycle counter is started.

The voltages at the VLDO and VOUT pins are then com-

pared; if the two voltages are within ±300mV (typically) of

each other, within 32 cylces, the VLDO pin connects to the

VOUT pin using an internal switch, and the LDO is turned

off.

In the second method, the DC-DC converter is already

running and the LDO is enabled. In this case the 32 cycles

are started as soon as the LDO reaches 90% of its final

value. At this time, the VLDO and VOUT pins are compared,

and if within ±300mV (typically) the switch-over occurs

and the LDO is turned off.

Switch-over Limitations on VOUT and VLDO

Because the internal switch-over circuit always compares

the VOUT and VLDO pins at start-up, there are voltage

limitations on permissible combinations of these pins.

Consider the situation where V is programmed to 4.7V.

OUT

After start-up, the device would connect VOUT to VLDO

and disable the LDO, since the two voltage are within the

±300mV switch-over window. To avoid unwanted switch-

over, the minimum difference between the voltages for

V and V should be ±500mV.

OUT

LDO

Switch-over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that

are inherent to its construction, as shown in Figure 11.

Switchover

control

VLDO

Switchover

MOSFET

VOUT

Parasitic diode

Parasitic diode

V5V

Figure 11— Switch-over MOSFET Parasitic Diodes

There are some important design rules that must be fol-

lowed to prevent forward bias of these diodes. The fol-

lowing two conditions need to be satisfied in order for the

parasitic diodes to stay off.

• V5V ≥ V

• LDO

V5V ≥ V

OUT

If either V or V is higher than V5V, then the respective

LDO

OUT

diode will turn on and the SC414/SC424 operating current

will flow through this diode. This has the potential of

damaging the device.

ENL pin and V UVLO

IN

The ENL pin also acts as the switcher under-voltage

lockout for the V supply. The V UVLO voltage is pro-

IN

IN

grammable via a resistor divider at the VIN, ENL, and AGND

pins.

ENL is the enable/disable signal for the LDO. In order to

implement the V UVLO there is also a timing requirement

IN

that needs to be satisfied.

If the ENL pin transitions low within 2 switching cycles and

is < 1V, then the LDO will turn off but the switcher remains

on. If ENL goes below the V UVLO threshold and stays

IN

above 1V, then the switcher will turn off but the LDO

remains on.

The V UVLO function has a typical threshold of 2.6V on

IN

the V rising edge. The falling edge threshold is 2.4V.

IN

20

Share Link: