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SC414

6A Integrated FET Regulator with 5V LDO

Semtech Corporation 

SC414/SC424

Applications Information (continued)

Note that it is possible to operate the switcher with the

LDO disabled, but the ENL pin must be below the logic

low threshold (0.4V maximum). The table below summa-

rizes the function of the ENL and EN pins, with respect to

the rising edge of ENL.

signal. If PGOOD is high, then the switcher is already

running and the LDO will run through the start-up cycle

without affecting the switcher. If PGOOD is low, then the

LDO will not allow any PWM switching until the LDO

output has reached 90% of it’s final value.

EN

ENL

LDO status Switcher status

low low, < 0.4V

off

off

high low, < 0.4V

off

on

low high, < 2.6V

on

off

high high, < 2.6V

on

off

low high, > 2.6V

on

off

high high, > 2.6V

on

on

Figure 12 below shows the ENL voltage thresholds and

their effect on LDO and Switcher operation.

ENL voltage

2.6V

2.4V

ENL low

threshold

(min 0.4V)

AGND

LDO on

Switcher on if EN = high

VIN UVLO hysteresis

LDO on

Switcher off by VIN UVLO

LDO off

Switcher on if EN = high

Figure 12 — ENL Thresholds

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6V, it is impossible to

determine if the LDO output is going to be used to power

the device or not. In self-powered operation where the

LDO will power the device, it is necessary during the LDO

start-up to hold the PWM switching off until the LDO has

reached 90% of the final value. This prevents overloading

the current-limited LDO output during the LDO start-up.

However, if the switcher was previously operating (with

EN/PSV high but ENL at ground, and V5V supplied exter-

nally), then it is undesirable to shut down the switcher. To

prevent this, when the ENL input is above 2.6V (above the

V UVLO threshold), the internal logic checks the PGOOD

IN

Using the On-chip LDO to Bias the SC414/SC424

The following steps must be followed when using the

internal LDO to bias the device.

• Connect V5V to VLDO before enabling the LDO.

• Any external load on VLDO should not exceed

40mA until the LDO voltage has reached 90% of

final value.

• Do not connect the EN pin directly to the V5V or

any other supply voltage if Vout is greater than

or equal to 4.5V

Many applications connect the EN pin to V5V and control

the on/off of the LDO and PWM simultaneously with the

ENL pin. This allows one signal to control both the bias

and power output of the SC414. When V > 4.5V this

OUT

configuration can cause problems due to the parasitic

diodes in the LDO switchover circuitry. After the Vout >

4.5V PWM output is up and running the switchover diodes

can hold up V5V > UVLO even if the ENL pin is grounded,

turning off the LDO. Operating in this way can potentially

damage the part.

Design Procedure

When designing a switch mode supply the input voltage

range, load current, switching frequency, and inductor

ripple current must be specified.

The maximum input voltage (V ) is the highest speci-

INMAX

fied input voltage. The minimum input voltage ( V ) is

INMIN

determined by the lowest input voltage after evaluating

the voltage drops due to connectors, fuses, switches, and

PCB traces.

The following parameters define the design.

• Nominal output voltage (V )

• OUT

Static or DC output tolerance

• Transient response

• Maximum load current (I )

OUT

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