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SC414

6A Integrated FET Regulator with 5V LDO

Semtech Corporation 

SC414/SC424

Applications Information (continued)

is recommended to force 33% of the V5V voltage on the

EN/PSV pin to operate in forced continuous mode.

When EN/PSV is high (above 45% of the voltage at V5V)

for SC414, the switching regulator turns on with ultrasonic

power-save enabled. The SC414 ultrasonic power-save

operation maintains a minimum switching frequency of

25kHz, for applications with stringent audio

requirements.

When EN/PSV is high (above 45% of the voltage at V5V)

for SC424, the switching regulator turns on with power-

save enabled. The SC424 power-save operation is designed

to maximize efficiency at light loads with no minimum

frequency limits. This makes the SC424 an excellent choice

for portable and battery-operated systems.

The ENL input is used to control the internal LDO. This

input provides a second function by acting as a V ULVO

IN

sensor for the switching regulator. When ENL is low

(grounded), the LDO is off. When ENL is a logic high but

below the V UVLO threshold (2.6V typical), then the LDO

IN

is on and the switcher is off. When ENL is above the V

IN

UVLO threshold, the LDO is enabled and the switcher is

also enabled if the EN/PSV pin is not grounded.

Forced Continuous Mode Operation

The SC414/SC424 operates the switcher in Forced

Continuous Mode (FCM) by floating the EN/PSV pin (see

Figure 4). In this mode of operation, the MOSFETs are

turned on alternately to each other with a short dead time

between them to avoid cross conduction. This feature

results in uniform frequency across the full load range

with the trade-off being poor efficiency at light loads due

to the high-frequency switching of the MOSFETs.

For V5V < 4.5V, it is recommended to force 33% of the V5V

voltage on the EN/PSV pin to operate in forced continuous

mode.

FB Ripple

Voltage (VFB)

Inductor

Current

FB threshold

(750mV)

DC Load Current

On-time DH on-time is triggered when

(TON) VFB reaches the FB Threshold.

DH

DL

DL drives high when on-time is completed.

DL remains high until VFB falls to the FB threshold.

Figure 4 — Forced Continuous Mode Operation

Ultrasonic Power-save Operation (SC414)

The SC414 provides ultrasonic power-save operation at

light loads, with the minimum operating frequency fixed

at slightly under 25kHz. This is accomplished by using an

internal timer that monitors the time between consecu-

tive high-side gate pulses. If the time exceeds 40μs, DL

drives high to turn the low-side MOSFET on. This draws

current from V through the inductor, forcing both V

OUT

OUT

and V to fall. When V drops to the 750mV threshold, the

FB

FB

next DH (the drive signal for the high side FET) on-time is

triggered. After the on-time is completed the high-side

MOSFET is turned off and the low-side MOSFET turns on.

The low-side MOSFET remains on until the inductor

current ramps down to zero, at which point the low-side

MOSFET is turned off.

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