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SC414

6A Integrated FET Regulator with 5V LDO

Semtech Corporation 

SC414/SC424

Applications Information (continued)

During soft-start the regulator turns off the low-side

MOSFET on any cycle if the inductor current falls to zero.

This prevents negative inductor current, allowing the

device to start into a pre-biased output. This soft start

operation is implemented even if FCM is selected. FCM

operation is allowed only after PGOOD is high.

Power Good Output

The power good (PGOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage

is 10% below the nominal voltage, PGOOD is pulled low. It

is held low until the output voltage returns to the nominal

voltage. PGOOD is held low during start-up and will not

be allowed to transition high until soft-start is completed

(when V reaches 750mV) and typically 4ms has passed.

FB

PGOOD will transition low if the V pin exceeds +20% of

FB

nominal, which is also the over-voltage shutdown thresh-

old (900mV). PGOOD also pulls low if the EN/PSV pin is

low when V5V is present.

Output Over-Voltage Protection

Over-Voltage Protection (OVP) becomes active as soon as

the device is enabled. The threshold is set at 750mV + 20%

(900mV). When V exceeds the OVP threshold, DL latches

FB

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off, until the EN/PSV input

is toggled or V5V is cycled. There is a 5μs delay built into

the OVP detector to prevent false transitions. PGOOD is

also low after an OVP event.

Output Under-Voltage Protection

When V falls to 75% of its nominal voltage (falls to

FB

562.5mV) for eight consecutive clock cycles, the switcher

is shut off and the DH and DL drives are pulled low to turn

off the MOSFETs. The controller stays off until EN/PSV is

toggled or V5V is cycled.

V5V UVLO, and POR

Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-

ing and tri-states the DH/DL drivers until V5V rises above

2.9V. An internal Power-On Reset (POR) occurs when V5V

exceeds 2.9V, which resets the fault latch and soft-start

counter to begin the soft-start cycle. The SC414/SC424

then begins a soft-start cycle. The PWM will shut off if V5V

falls below 2.7V.

LDO Regulator

The device features an integrated LDO regulator with a

fixed output voltage of 5V. There is also an enable pin

(ENL) for the LDO that provides independent control. The

LDO voltage can also be used to provide the bias voltage

for the switching regulator.

A minimum capacitance of 1μF referenced to AGND is

normally required at the output of the LDO for stability. If

the LDO is providing bias power to the device, then a

minimum 0.1μF capacitor referenced to AGND is required,

along with a minimum 1μF capacitor referenced to PGND

to filter the gate drive pulses. Refer to the layout guide-

lines section.

LDO Start-up

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

1. ENL pin

2. VLDO output

3. V input voltage

IN

When the ENL pin is high, the LDO will begin start-up, see

Figure 10. During the initial phase, when the LDO output

voltage is near zero, the LDO initiates a current-limited

start-up (typically 85mA) to charge the output capacitor.

When V has reached 90% of the final value, the LDO

LDO

current limit is increased to ~200mA and the LDO output

is quickly driven to the nominal value by the internal LDO

regulator.

VVLDO Final

90% of VVLDO Final

Voltage regulating with

~200mA current limit

Constant current startup

Figure 10 — LDO Start-Up

19

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