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NJU8721

CLASS D HEADPHONE AMPLIFIER FOR DIGITAL AUDIO

Japan Radio Corporation  

NJU8721

(8) Control Register

When Control Mode is set to Serial control by the Mode terminal, the control register sets various modes.

The Control Data is fetched by the rising edge of F2/SCK and is set into the control register by the rising edge of

F1/REQ. The latest 8 bits data are valid before the F1/REQ rising pulse.

F1/REQ

F2/SCK

F0/DATA

B7

B6

B5

B4

B3

B2

B1

B0

Figure 5. Control Register Timing

(8-1) Serial Data Format

B7

B6

B5

B4

0

ATTN6 ATTN5 ATTN4

1

0

0

0

1

0

0

1

1

0

1

0

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

Do not set other data excepting this table.

B3

ATTN3

0

F2

0

0

0

0

0

B2

ATTN2

0

F1

0

0

0

MUTT2

0

B1

ATTN1

DEMP1

F0

0

0

0

MUTT1

0

B0

ATTN0

DEMP0

MUTE

RST

TEST

0

MUTT0

TRST

(8-2) ATTN6 to ATTN0

When B7 is “0”, B0 to B6 set the attenuation data. When attenuation data is set, the attenuation value

is changed to the target value in the period of transition time set by MUTT0 to MUTT2. The attenuation

value (ATT) is fixed by following formula.

When ATT is 14h or less, the attenuator is set -∞ at reset. (When Control Mode is Parallel Control, ATT is

fixed 0db.)

ATT=DATA -121[dB]

DATA : attenuation point

7Fh=6dB

7Eh=5dB

7Dh=4dB

:

79h=0dB

:

16h=-99dB

15h=-100dB

14h=-∞

13h=-∞

:

00h=-∞ (initial value)

-7-

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