LTC6603 Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

Fabricante

LTC6603

Dual Adjustable Lowpass Filter

Linear Technology 

LTC6603

PIN FUNCTIONS

LPF1(CS) (Pin 6): TTL Level Input. When in pin program-

mable control mode, this pin is the MSB of the lowpass

cutoff frequency control code; in serial control mode, this

pin is the chip select input (active low).

+INB, –INB (Pins 7, 8): Channel B differential inputs.

The input range and input resistance are described in the

Applications Information section. Input voltages which

exceed V+IN (Pin 1) should be avoided.

LPF0(SCLK) (Pin 9): TTL Level Input. When in pin program-

mable control mode, this pin is the LSB of the lowpass

cutoff frequency control code; in serial control mode, this

pin is the clock of the serial interface.

SDI (Pin 10): TTL Level Input. When in pin programmable

control mode, this pin is left floating; in serial control

mode, this pin is the serial data input.

SDO (Pin 11): TTL Level Input. When in pin programmable

control mode, this pin is left floating; in serial control

mode, this pin is the serial data output.

–OUTB, +OUTB (Pins 12, 13): Channel B differential filter

outputs. These pins can drive 1k and/or 50pF loads. For

larger capacitive loads, an external 100Ω series resistor

is recommended for each output. The common mode

voltage of the filter outputs is the same as the voltage at

VOCM (Pin 3).

GND (Pin 14): Ground. Should be tied to a ground plane

for best performance.

CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground,

CLKIO is the master clock input. When CLKCNTL is floated,

CLKIO is pulled to ground by a weak pulldown. When

CLKCNTL is tied to V+D (Pin 16), CLKIO is the master

clock output. When configured as a clock output, this pin

can drive 1k and/or 5pF loads (heavier loads will cause

inaccuracies).

V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V).

This supply must be kept free from noise and ripple. It

should be bypassed directly to a ground plane with a 0.1μF

capacitor. The bypass should be as close as possible to

the IC.

SER (Pin 17): Interface Selection Input. When tied to V+D

(Pin 16) or floated, the interface is in pin programmable

control mode, i.e. the filter gain and cutoff frequencies

are programmed by the GAIN1, GAIN0, LPF1 and LPF0

pins. When SER is tied to ground, the filter gain, the filter

cutoff frequency and shutdown mode are programmed

by the serial interface.

–OUTA, +OUTA (Pins 18, 19): Channel A differential filter

outputs. These pins can drive 1k and/or 50pF loads. For

larger capacitive loads, an external 100Ω series resistor

is recommended for each output. The common mode

voltage of the filter outputs is the same as the voltage at

VOCM (Pin 3).

CAP (Pin 20): Connect a 0.1μF bypass capacitor to this

pin. Pin 20 is a buffered version of Pin 3.

GAIN0(D0) (Pin 21): TTL Level Input. When in pin pro-

grammable control mode, this pin is the LSB of the gain

control code; in serial control mode, this pin is the LSB

of the serial control register, an output.

GAIN1 (Pin 22): TTL Level Input. When in pin programmable

control mode, this pin is the MSB of the gain control code;

in serial control mode, this pin is a no-connect.

–INA, +INA (Pins 23, 24): Channel A differential inputs.

The input range and input resistance are described in the

Applications Information section. Input voltages which

exceed V+IN (Pin 1) should be avoided.

Exposed Pad (Pin 25): Ground. The Exposed Pad must

be soldered to PCB.

6603f

11

Share Link: