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LTC6603

Dual Adjustable Lowpass Filter

Linear Technology 

LTC6603

APPLICATIONS INFORMATION

Theory of Operation (Refer to Block Diagram)

The LTC6603 features two matched filter channels, each

containing gain control and lowpass filter networks that

are controlled by a single control block and clocked by

a single clock generator. The gain and cutoff frequency

can be separately programmed. The two channels are

not independent, i.e. if the gain is set to 24dB then both

channels have a gain of 24dB. The filter can be clocked

with an external clock source, or using the internal oscil-

lator. A resistor connected to the RBIAS pin sets the bias

currents for the filter networks and the internal oscillator

frequency (unless driven by an external clock). Altering the

clock frequency changes the filter bandwidth. This allows

the filters to be “tuned” to many different bandwidths.

Pin Programmable Interface

As shown in Figure 1, connecting SER to V+D allows the

filter to be directly controlled through the pin program-

mable control lines GAIN1, GAIN0, LPF1 and LPF0. The

GAIN0(D0) pin is bidirectional (input in pin programmable

control mode, output in serial mode). In pin programmable

control mode, the voltage at GAIN0(D0) cannot exceed V+D;

otherwise, large currents can be injected to V+D through the

parasitic diodes (see Figure 2). Connecting a 10k resistor

at the GAIN0(D0) pin (see Figure 1) is recommended for

current limiting, to less than 10mA. SER has an internal

pull-up to V+D. None of the logic inputs have an internal

pull-up or pull-down.

Serial Interface

Connecting SER to ground allows the filter to be controlled

through the SPI serial interface. When CS is low, the serial

data on SDI is shifted into an 8-bit shift-register on the

rising edge of the clock (SCLK), with the MSB transferred

first (see Figure 3). Serial data on SDO is shifted out on

the clock’s falling edge. A high CS will load the 8 bits of

the shift-register into an 8-bit D-latch, which is the serial

control register. The clock is disabled internally when

CS is pulled high. Note: SCLK must be low before CS is

pulled low to avoid an extra internal clock pulse. SDO is

always active in serial mode (never tri-stated) and cannot

be “wire-or’ed” to other SPI outputs. In addition, SDO is

not forced to zero when CS is pulled high.

An LTC6603 may be daisy chained with other LTC6603s

or other devices having serial interfaces. Daisy chain-

ing is accomplished by connecting the SDO of the lead

chip to the SDI of the next chip, while SCLK and CS

remain common to all chips in the daisy chain. The se-

rial data is clocked to all the chips then the CS signal

is pulled high to update all of them simultaneously.

Figure 4 shows an example of two LTC6603s in a daisy

chained SPI configuration.

3.3V

0.1μF

+

VIN

–

LTC6603

V+IN

V+A

V+D

+INA

+OUTA

–INA

SER

LPF1(CS)

LPF0(SCLK)

–OUTA

+

VOUT

–

GAIN1

GAIN0(D0)

GND

3.3V

0.1μF

+

VIN

–

LPF1

LPF0

μP

GAIN1

GAIN0

10k

LTC6603

V+IN

V+A

V+D

+INA

+OUTA

–INA

SER

LPF1(CS)

LPF0(SCLK)

–OUTA

+

VOUT

–

GAIN1

GAIN0(D0)

GND

LOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz)

GAIN = 4

GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.

10k RESISTORS ON GAIN0(OUT) PROTECTS THE

DEVICE WHEN VGAIN0 > V+D

6603 F01

Figure 1. Filter in Pin Programmable Control Mode

6603f

13

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