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LTC6603

Dual Adjustable Lowpass Filter

Linear Technology 

LTC6603

APPLICATIONS INFORMATION

results in four matched filter channels, all synchronized to

the same clock. The master has its CLKCNTL pin pulled

to V+D, configuring its CLKIO pin as an output, while the

slave has its CLKCNTL pin pulled to ground, configuring its

CLKIO pin as an input. Note that in order to synchronize the

two filters, the clock frequency must not be buffered. This

requires that the filters be close together on the PC board.

If the clock is buffered, the filters would have matching

bandwidths, but would not be synchronized.

Output Drive

The filter outputs can drive 1k and/or 50pF loads connected

to AC ground with a 0.5V to 2.5V signal (corresponding

to a 4VP-P differential signal). For differential loads (loads

connected between +OUTA and –OUTA or +OUTB and

–OUTB) the outputs can produce a 4VP-P signal across 2k

and/or 25pF. For smaller signal amplitudes, the outputs can

drive correspondingly larger loads. For larger capacitive

loads, an external 50Ω series resistor is recommended

for each output.

Clock Feedthrough

Clock feedthrough is defined as the RMS value of the clock

frequency and its harmonics that are present at the filter’s

output. The clock feedthrough is measured with +INA and

–INA (or +INB, –INB) tied to VOCM and depends on the PC

board layout and the power supply decoupling. The clock

feedthrough can be reduced with a simple RC post filter.

Decoupling Capacitors

The LTC6603 uses sampling techniques, therefore its

performance is sensitive to supply noise. 0.1μF ceramic

decoupling capacitors must be connected from V+A (Pin 2)

and V+D (Pin 16) to ground with leads as short as possible.

A ground plane should be used. Noisy signals should be

isolated from the filter’s input pins. In addition, a 0.1μF

decoupling capacitor at Pin 20 is recommended since this

pin receives clocked current injection.

Aliasing

Aliasing is an inherent phenomenon of sampled data filters.

Significant aliasing only occurs when the frequency of the

input signal approaches the sampling frequency or mul-

tiples of the sampling frequency. The ratio of the LTC6603

input sampling frequency to the clock frequency, fCLK, is

determined by the state of control bits LPF1 and LPF0.

Table 6 shows the possible input sampling frequencies for

a clock frequency of 80MHz. The input sampling frequency

is proportional to the clock frequency. For example, if the

clock frequency is lowered from 80MHz to 40MHz, the

input sampling frequency will be lowered by half. Input

signals with frequencies near the input sampling frequency

will be aliased to the passband of the filter and appear at

the output unattenuated.

Table 6. Input Sampling Frequency (fCLK = 80MHz)

LPF1

LPF0

Input Sampling Frequency (MHz)

0

0

20

0

1

40

1

0

160

1

1

160

A simple LC anti-aliasing filter is recommended at the

filter inputs to attenuate frequencies near the input sam-

pling frequency that will be aliased to the passband. For

example, if the clock frequency is set to 80MHz and the

cutoff frequency of the filter is set to its maximum (LPF1

= ‘1’), the lowest frequency that would be aliased to the

passband would be fCLK – fCUTOFF, i.e. 160MHz – 2.5MHz

= 157.5MHz. The LTC6603 filter inputs should be driven

by a low impedance output (<100Ω).

Wideband Noise

The wideband noise of the filter is the RMS value of the

device’s output noise spectral density. The wideband noise

is nearly independent of the value of the clock frequency

and excludes the clock feedthrough. Most of the wideband

noise is concentrated in the filter passband and cannot be

removed with post filtering.

Power Supply Current

The power supply current depends on the state of the

lowpass cutoff frequency controls (LPF1, LPF0) and the

value of RBIAS. When the LTC6603 is programmed for

the middle cutoff frequency (LPF1 = ‘0’, LPF0 = ‘1’), the

supply current is reduced by about 23% relative to the

supply current for the higher bandwidth setting. Pro-

6603f

21

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