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LT3582EUD Ver la hoja de datos (PDF) - Linear Technology

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LT3582EUD Datasheet PDF : 28 Pages
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LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Output Disconnect Operating Limits
The LT3582 series has a PMOS output disconnect switch
connected between CAPP and VOUTP. During normal
operation, the switch is closed and current is internally
limited to about 155mA (see Figure 9). Make sure that
the output load current doesn’t exceed the PMOS current
limit. Exceeding the current limit causes a significant
rise in PMOS power consumption which may damage
the device.
During shutdown, the PMOS switch is open and CAPP is
isolated from VOUTP up to a voltage difference of 5-5.5V.
In most cases this allows VOUTP to discharge to ground.
However, when the Boost inductor input exceeds 5.5V,
the CAPP-VOUTP voltage may exceed 5V allowing some
current flow through the PMOS switch. In addition, apply-
ing CAPP-VOUTP voltages in excess of 5.7V(typical) may
activate internal protection circuitry which turns the PMOS
“on” (see Figure 10). If the current is not limited, this can
lead to a sharp increase in the PMOS power consumption
and may damage the device. If this situation cannot be
avoided, limit PMOS power consumption to less than 1/3
Watt (about 50mA at 7V) to avoid damaging the device.
Refer to the Absolute Maximum Ratings table for maximum
limits on CAPP-VOUTP voltages and currents.
Improving Boost Converter Efficiency
The efficiency of the Boost converter can be improved by
shorting the CAPP pin to the VOUTP pin (see Figure 11). The
power loss in the PMOS disconnect circuit is then made
negligible. In most applications, the associated CAPP pin
capacitor can be removed and the larger VOUTP capacitor
can adequately filter the output voltage.
Note that the ripple voltage on VOUTP will typically in-
crease in this configuration since the output disconnect
PMOS, when not shorted, helps to create an RC filter at
the output. Also, if the VOUTP pin is shorted to CAPP,
the power-down discharge should not be enabled. VOUTP
cannot be discharged to ground during shutdown due to
the path from VIN to VOUTP through the external inductor
ICAPP-VOUTP
20μA/DIV
180
160
140
120
100
80
60
40
20
0
0
100 200 300 400 500
CAPP-VOUTP (mV)
3582512 F10
Figure 9: PMOS Current vs. Voltage During Normal Operation
VCAPP-VOUTP 1V/DIV
3582512 F11
Figure 10: PMOS Current vs. Voltage During Shutdown
4 SWN
3
SWN
SWP 12
VIN 5
13 GND
LT3582
CAPP 11
CAPP 10
VOUTP 9
2
VOUTN
VPP 14
SDA 15
SCL 16
8 SHDN
CA 1
RAMPP RAMPN
7
6
3582512 F12
C1
ILOAD
Figure 11: Improved Efficiency
20
3582512f

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