CY22801KSXC-XXX(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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Fabricante

CY22801KSXC-XXX
(Rev.:2011)

Universal Programmable Clock Generator (UPCG)

Cypress Semiconductor 

CY22801

Application Guideline

Best Practices for Best Jitter Performance

Jitter can be specified in different terminologies:

Time Domain:

■ Cycle-to-cycle jitter

■ Period jitter

■ Long-term jitter

Frequency domain:

■ Deterministic jitter

■ Random jitter

■ Phase noise

These jitter terms are usually given in terms of root mean square

(RMS), peak-to-peak, or in the case of phase noise, dBC/Hz with

respect to fundamental frequency. Cycle-to-cycle and period

jitter are generally used terminologies. Jitter depends on many

factors and few of the them can be controlled in application:

■ Input reference jitter

■ Number of active clock outputs

■ Operating temperature

■ Clock output load

■ PLL frequencies

■ Termination and layout

■ Supply voltage accuracy

Jitter is directly proportional to the input reference jitter, number

of active clock outputs, operating temperature and clock output

load, but inversely proportional to the PLL frequency. Best

practices for termination, layout and supply voltage filtering are

discussed in application note “Layout and Termination

Techniques For Cypress Clock Generators-AN1111”.

Field Programming the CY22801

The CY22801 is programmed using the CY36800 USB

programmer dongle. The CY22801 is flash-technology based, so

the parts are reprogrammed up to 100 times. This enables fast

and easy design changes and product updates, and eliminates

any issues with old and out-of-date inventory.

Samples and small prototype quantities are programmed using

the CY36800 programmer. Cypress’s value-added distribution

partners and third-party programming systems from BP

Microsystems, HiLo Systems, and others, are available for large

production quantities.

CyClocksRT Software

CyClocksRT is an easy-to-use software application that enables

the user to custom-configure the CY22801. Users can specify

the XIN/CLKIN frequency, crystal load capacitance, and output

frequencies. CyClocksRT then creates an industry-standard

JEDEC file that is used to program the CY22801.

When needed, an advanced mode is available that enables

users to override the automatically generated voltage controlled

oscillator (VCO) frequency and output divider values.

CyClocksRT is a component of the CyberClocks™ software that

you can download free of charge from the Cypress website at

http://www.cypress.com.

CY36800 InstaClock™ Kit

The Cypress CY36800 InstaClock kit comes with everything

needed to design the CY22801 and program samples and small

prototype quantities. The CyClocksRT software is used to

quickly create a JEDEC programming file, which is then

downloaded directly to the portable programmer that is included

in the CY36800 InstaClock kit. The JEDEC file can also be saved

for use in a production programming system for larger volumes.

The CY36800 also comes with five samples of the CY22801,

which are programmed with preconfigured JEDEC files using the

InstaClock software.

Possible Configuration Examples

Table 16. Possible Configuration

Possible

Configurations

A

Pin#1

CLKIN:33 MHz

B

XIN:27 MHz

crystal

C

CLKIN:10 MHz

D

CLKIN:10 MHz

Pin#3

OE

VCXO

OE

SDAT

Pin#5

Pin#6

Pin#7

Pin#8

CLKB: 33 MHz CLKA:100 MHz with

+/-1% Spread

SSON

PD#

CLKA: 74.25

FS2

/74.175824 MHz

FS1

CLKA:

FS2

25/40/33.3333/50 MHz

SCLK

CLKA

CLKB

NC

XOUT: 27

MHz crystal

NC

NC

Contact your local Cypress field application engineer for functional feasibility and custom configuration with these advanced features.

Document #: 001-15571 Rev. *E

Page 11 of 23

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