CY22801KSXC-XXX(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY22801KSXC-XXX
(Rev.:2011)

Universal Programmable Clock Generator (UPCG)

Cypress Semiconductor 

CY22801

Figure 15. Start and Stop Frame

START

Transition

to next bit

STOP

SDAT

SCLK

Figure 16. Frame Format (Device Address, R/W, Register Address, Register Data

SDAT

+

+

+

START DA6 DA5DA0 R/W ACK RA7 RA6RA1 RA0 ACK D7 D6 D1 D0 ACK

SCLK

+

+

+

STOP

Table 17. Two-wire Serial Interface Parameters

Parameter

Description

Min

Max

Unit

fSCLK

Frequency of SCLK

–

400

kHz

Start mode time from SDA LOW to SCL LOW

0.6

–

μs

CLKLOW

CLKHIGH

tSU

tDH

SCLK LOW period

SCLK HIGH period

Data transition to SCLK HIGH

Data hold (SCLK LOW to data transition)

Rise time of SCLK and SDAT

1.3

–

μs

0.6

–

μs

100

–

ns

100

–

ns

–

300

ns

Fall time of SCLK and SDAT

–

300

ns

Stop mode time from SCLK HIGH to SDAT HIGH

0.6

–

μs

Stop mode to start mode

1.3

–

μs

Document #: 001-15571 Rev. *E

Page 18 of 23

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