CY22801KSXC-XXX(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY22801KSXC-XXX
(Rev.:2011)

Universal Programmable Clock Generator (UPCG)

Cypress Semiconductor 

CY22801

DC Electrical Specifications[6]

Parameter

IOH

IOL

CIN1

CIN2

Name

Output high current

Output low current

Input capacitance

Input capacitance

IIH

IIL

fΔXO

VVCXO

VIH

VIL

IDD[7]

Input high current

Input low current

VCXO pullability range

VCXO input range

Input high voltage

Input low voltage

VDD supply current

Description

VOH = VDD – 0.5, VDD = 3.3 V (source)

VOL = 0.5, VDD = 3.3 V (sink)

All input pins except XIN and XOUT

XIN and XOUT pins for non-VCXO

applications

VIH = VDD

VIL = 0 V

Using crystal in this datasheet

CMOS levels, 70% of VDD

CMOS levels, 30% of VDD

All three clock outputs are at 100 MHz

Min

Typ Max Unit

12

24

–

mA

12

24

–

mA

–

–

7

pF

–

24

–

pF

–

5

10

μA

–

–

50

μA

±150

–

ppm

0

–

VDD

V

0.7 × VDD –

–

V

–

– 0.3 × VDD V

–

30

–

mA

AC Electrical Characteristics

Parameter[6]

Name

Description

Min

fREFC

Reference frequency - crystal

8

fREFD

Reference frequency - driven

1

fOUT

Output frequency, commercial

1

grade

Output frequency, industrial

1

grade

DC

Output duty cycle

50% of VDD, see Figure 6

45

t3

Rising edge slew rate

Output clock rise time, 20% - 80% of VDD,

0.8

see Figure 7

t4

Falling edge slew rate

Output clock fall time, 80% - 20% of VDD, see 0.8

Figure 7

t5[8]

Skew

Output-output skew between related

–

outputs, see Figure 9

t6[9]

tCCJ[9]

Clock jitter

Cycle-to-cycle jitter

CLKA/B/C

tPD

Power-down time

Peak-to-peak period jitter, see Figure 8

–

XIN = CLKA/B/C = 166 MHz, ± 2% spread

–

and No REFOUT, VDD = 3.3 V, see Figure 10

XIN = CLKA/B/C = 66.66 MHz, ± 2% spread

–

and No REFOUT, VDD = 3.3 V, see Figure 10

XIN = CLKA/B/C = 33.33 MHz, ± 2% spread

–

and No REFOUT, VDD = 3.3 V, see Figure 10

XIN = CLKA/B/C = 14.318 MHz, ± 2% spread

–

and No REFOUT, VDD = 3.3 V, see Figure 10

Time from falling edge on PD# Pin to tristated

–

outputs (Asynchronous), see Figure 11

Typ Max Unit

–

30 MHz

–

133 MHz

–

200 MHz

–

166.6 MHz

50

55

%

1.4

–

V/ns

1.4

–

V/ns

–

250

ps

250

–

ps

–

110

ps

–

170

ps

–

140

ps

–

290

ps

150

300

ns

Notes

6. Not 100% tested, guaranteed by design.

7. Power supply current is configuration dependent. Use CyClocksRT to calculate actual IDD for specific output frequency configurations.

8. Skew value guaranteed when outputs are generated from the same divider bank.

9. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage,

temperature, and output load.

Document #: 001-15571 Rev. *E

Page 14 of 23

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