CY14B256L-ZS25XI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B256L-ZS25XI Datasheet PDF : 22 Pages
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CY14B256LA
AC Switching Characteristics
Over the Operating Range
Parameters [14]
Cypress
Alt
Parameters Parameters
SRAM Read Cycle
tACE
tACS
tRC[15]
tRC
tAA[16]
tAA
tDOE
tOE
tOHA[16]
tOH
tLZCE[17, 18]
tLZ
tHZCE[17, 18]
tHZ
tLZOE[17, 18]
tOLZ
tHZOE[17, 18]
tOHZ
tPU[17]
tPA
tPD[17]
tPS
SRAM Write Cycle
tWC
tWC
tPWE
tWP
tSCE
tCW
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tWR
tHZWE[17, 18, 19] tWZ
tLZWE[17, 18]
tOW
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
25 ns
Min
Max
–
25
25
–
–
25
–
12
3
–
3
–
–
10
0
–
–
10
0
–
–
25
25
–
20
–
20
–
10
–
0
–
20
–
0
–
0
–
–
10
3
–
45 ns
Min
Max
Unit
–
45
ns
45
–
ns
–
45
ns
–
20
ns
3
–
ns
3
–
ns
–
15
ns
0
–
ns
–
15
ns
0
–
ns
–
45
ns
45
–
ns
30
–
ns
30
–
ns
15
–
ns
0
–
ns
30
–
ns
0
–
ns
0
–
ns
–
15
ns
3
–
ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1 (Address Controlled) [15, 16, 20]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
tOHA
Output Data Valid
Notes
14.
Test conditions assume signal transition time of
IOL/IOH and load capacitance shown in Figure .
3
ns
or
less,
timing
reference
levels
of
VCC/2,
input
pulse
levels
of
0
to
VCC(typ),
and
output
loading
of
the
specified
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE and OE LOW.
17. These parameters are guaranteed by design and are not tested.
18. Measured ±200 mV from steady state output voltage.
19. If WE is low when CE goes low, the outputs remain in the high impedance state.
20. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-54707 Rev. *I
Page 11 of 22
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