CY14B256L-ZS25XI Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY14B256L-ZS25XI

256-Kbit (32 K × 8) nvSRAM

Cypress Semiconductor 

CY14B256LA

Hardware STORE Cycle

Over the Operating Range

Parameters

Description

tDHSB

tPHSB

tSS [34, 35]

HSB to output active time when write latch is not set

Hardware STORE pulse width

Soft sequence processing time

CY14B256LA

Min

Max

Unit

–

25

ns

15

–

ns

–

100

s

Switching Waveforms

Write latch set

HSB (IN)

tPHSB

HSB (OUT)

tDELAY

DQ (Data Out)

Figure 12. Hardware STORE Cycle [36]

tSTORE

tHHHD

tLZHSB

RWI

Write latch not set

tPHSB

HSB (IN)

HSB (OUT)

RWI

tDELAY

tDHSB

tDHSB

HSB pin is driven high to VCC only by Internal

100 kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

Figure 13. Soft Sequence Processing [34, 35]

Address

CE

VCC

Soft Sequence

tSS

Command

Address #1

tSA

Address #6

tCW

Soft Sequence

tSS

Command

Address #1

Address #6

tCW

Notes

34. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

35. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

36. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

Document Number: 001-54707 Rev. *I

Page 15 of 22

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