Switching Waveforms (continued)
Figure 6. SRAM Read Cycle #2 (CE and OE Controlled) [21, 22]
Address
CE
OE
Data Output
ICC
Address
CE
WE
Data Input
Data Output
Address
Address Valid
tRC
tACE
tHZCE
tAA
tLZCE
tDOE
tHZOE
High Impedance
tLZOE
tPU
Output Data Valid
tPD
Standby
Active
Figure 7. SRAM Write Cycle #1 (WE Controlled) [22, 23, 24]
tWC
Address Valid
tSCE
tHA
tAW
tPWE
tSA
tSD
tHD
tHZWE
Input Data Valid
tLZWE
Previous Data
High Impedance
Figure 8. SRAM Write Cycle #2 (CE Controlled) [22, 23, 24]
tWC
Address Valid
tSA
tSCE
tHA
CE
tPWE
WE
tSD
tHD
Data Input
Input Data Valid
Data Output
High Impedance
Notes
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during READ and WRITE cycles.
23. If WE is low when CE goes low, the outputs remain in the high impedance state.
24. CE or WE must be > VIH during address transitions.
Document Number: 001-54707 Rev. *I
CY14B256LA
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