CY14B256LA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 2. Truth Table
CE
WE
OE
H
X
X
L
H
L
L
H
H
L
L
X
Inputs/Outputs
High Z
Data out (DQ0–DQ7);
High Z
Data in (DQ0–DQ7);
Mode
Deselect/power-down
Read
Output disabled
Write
Ordering Information
Speed
(ns)
Ordering Code
25 CY14B256LA-ZS25XIT
CY14B256LA-ZS25XI
CY14B256LA-SP25XIT
CY14B256LA-SP25XI
CY14B256LA-SZ25XIT
CY14B256LA-SZ25XI
45 CY14B256LA-SP45XIT
CY14B256LA-SP45XI
CY14B256LA-SZ45XIT
CY14B256LA-SZ45XI
All the above parts are Pb-free.
Ordering Code Definitions
CY 14 B 256 L A - ZS 25 X I T
Pb-free
Package Diagram
Package Type
51-85087
51-85087
51-85061
51-85061
51-85127
51-85127
51-85061
51-85061
51-85127
51-85127
44-pin TSOP II
44-pin TSOP II
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
Option:
T - Tape and Reel
Blank – Std.
Temperature:
I - Industrial (–40 to 85 °C)
Die revision:
Blank – No Rev
A – 1st Rev
Voltage:
B – 3.0 V
Package:
ZS - 44-pin TSOP II
SP - 48-pin SSOP
SZ - 32-pin SOIC
Density:
256 – 256 Kb
Data Bus:
L–×8
Power
Standby
Active
Active
Active
Operating Range
Industrial
Speed:
25 – 25 ns
45 – 45 ns
14 – nvSRAM
Cypress
Document Number: 001-54707 Rev. *I
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