CDP1802AC/3 Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
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CDP1802AC/3 Datasheet PDF : 27 Pages
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CDP1802AC/3
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
0
1
2
3
4
CLOCK
5
6
7
0
1
2
3
4
5
6
7
0
TPA
TPB
MACHINE
CYCLE
CYCLE n
CYCLE (n + 1)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
MRD
N0 - N2
MWR
MEMORY
OUTPUT
DATA
BUS
(NOTE)
N=9-F
ALLOWABLE MEMORY ACCESS
MEMORY READ CYCLE
VALID OUTPUT
VALID DATA FROM INPUT DEVICE
MEMORY WRITE CYCLE
NOTE: USER GENERATED SIGNAL
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 8. INPUT CYCLE TIMING WAVEFORMS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
CLOCK
TPA
TPB
MACHINE
CYCLE
CYCLE n
CYCLE (n + 1)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
MRD
N0 - N2
N=1-9
ALLOWABLE MEMORY ACCESS
DATA BUS
DATA STROBE
(MRD ² TPB ² N)
(NOTE)
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
VALID DATA FROM MEMORY
MEMORY READ CYCLE
MEMORY READ CYCLE
NOTE: USER GENERATED SIGNAL
“DON’T CARE” OR INTERNAL DELAYS
FIGURE 9. OUTPUT CYCLE TIMING WAVEFORMS
HIGH IMPEDANCE STATE
FN1441 Rev 3.00
October 17, 2008
Page 11 of 27
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