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CDP1802AC/3

High-Reliability CMOS 8-Bit Microprocessor

Intersil 

CDP1802AC/3

Signal Descriptions

Bus 0 to Bus 7 (Data Bus)

8-bit bidirectional DATA BUS lines. These lines are used for

transferring data between the memory, the microprocessor,

and I/O devices.

N0 to N2 (I/O Control Lines)

Activated by an I/O instruction to signal the I/O control logic of

a data transfer between memory and I/O interface. These

lines can be used to issue command codes or device

selection codes to the I/O devices (independently or

combined with the memory byte on the data bus when an I/O

instruction is being executed). The N bits are low at all times

except when an I/O instruction is being executed. During this

time their state is the same as the corresponding bits in the N

register.

The direction of data flow is defined in the I/O instruction by

bit N3 (internally) and is indicated by the level of the MRD

signal.

MRD = VCC: Data from I/O to CPU and Memory

MRD = VSS: Data from Memory to I/O

EF1 to EF4 (4 Flags)

These inputs enable the I/O controllers to transfer status

information to the processor. The levels can be tested by the

conditional branch instructions. They can be used in

conjunction with the INTERRUPT request line to establish

interrupt priorities. These flags can also be used by I/O

devices to “call the attention” of the processor, in which case

the program must routinely test the status of these flag(s).

The flag(s) are sampled at the beginning of every S1 cycle.

INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests)

These inputs are sampled by the CPU during the interval

between the leading edge of TPB and the leading edge of

TPA.

Interrupt Action - X and P are stored in T after executing

current instruction; designator X is set to 2; designator P is

set to 1; interrupt enable is reset to 0 (inhibit); and instruction

execution is resumed. The interrupt action requires one

machine cycle (S3).

DMA Action - Finish executing current instruction; R(0)

points to memory area for data transfer; data is loaded into

or read out of memory; and increment R(0).

NOTE: In the event of concurrent DMA and Interrupt requests,

DMA-lN has priority followed by DMA-OUT and then Interrupt.

SC0, SC1 (2 State Code Lines)

These outputs indicate that the CPU is:

1. Fetching an instruction

2. Executing an instruction

3. Processing a DMA request,

FN1441 Rev 3.00

October 17, 2008

4. acknowledging an interrupt request. The levels of state

code are tabulated in Table 1. All states are valid at TPA.

H = VCC, L = VSS.

TABLE 1. LEVELS OF STATE CODE

STATE CODE LINES

STATE TYPE

SC1

SC0

S0 (Fetch)

L

L

S1 (Execute)

L

H

S2 (DMA)

H

L

S3 (Interrupt)

H

H

TPA, TPB (2 Timing Pulses)

Positive pulses that occur once in each machine cycle (TPB

follows TPA). They are used by I/O controllers to interpret

codes and to time interaction with the data bus. The trailing

edge of TPA is used by the memory system to latch the

higher-order byte of the 16-bit memory address. TPA is

suppressed in IDLE when the CPU is in the load mode.

MA0 to MA7 (8 Memory Address Lines)

In each cycle, the higher-order byte of a 16-bit CPU memory

address appears on the memory address lines MA0-7 first.

Those bits required by the memory system can be strobed

into external address latches by timing pulse TPA. The low

order byte of the 16-bit address appears on the address lines

after the termination of TPA. Latching of all 8 higher-order

address bits would permit a memory system of 64k bytes.

MWR (Write Pulse)

A negative pulse appearing in a memory-write cycle, after

the address lines have stabilized.

MRD (Read Level)

A low level on MRD indicates a memory read cycle. It can be

used to control three-state outputs from the addressed

memory which may have a common data input and output

bus. If a memory does not have a three-state

high-impedance output, MRD is useful for driving

memory/bus separator gates. It is also used to indicate the

direction of data transfer during an I/O instruction. For

additional information see Table 4.

Q

Single bit output from the CPU which can be set or reset

under program control. During SEQ or REQ instruction

execution, Q is set or reset between the trailing edge of TPA

and the leading edge of TPB.

CLOCK

Input for externally generated single-phase clock. The clock

is counted down internally to 8-clock pulses per machine

cycle.

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