MU9C3640L-90TZC Ver la hoja de datos (PDF) - Music Semiconductors
Número de pieza
componentes Descripción
Fabricante
MU9C3640L-90TZC Datasheet PDF : 20 Pages
| |||
LIST-XL
OPERATIONAL CHARACTERISTICS Continued
Cycle Type
Op-Code
Command read
Command write
Command write
Command write
Command write
Command write
Command write
TCO CT
0000H
TCO CT
8040H
TCO SC
3808H
Command write SPS M@HM
Control Bus
/E /CM /W
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Comments
Notes
Clears power-up anomalies
Target Control register for reset
Causes reset
1
Target Control register for initial values
Control register value
2
Target Segment Counter Control register
Set Segment Counters to write to Segment 1, 2, and 3 and read
from Segment 0.
Set Data Reads from Segment 0 of the Highest-priority match
Notes:
1. A software reset using a TCO CT followed by 0000H puts the device in a known state. Good programming practice dictates a
software reset for initialization to account for all possible conditions.
2. A typical LIST-XL control environment: 48 CAM bits, 16 RAM bits; Disable comparison masking; and Enable address
increment. See Table 7 for Control Register bit assignments.
Table 5: Example Initialization Routine
INSTRUCTION SET DESCRIPTIONS*
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
f
Address Field flag†
sss
Selected source
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with “aaaH” and the
first access to that persistent source will be at aaaH, after
which the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the same
except the current Address Register value is used.
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
f
Address Field flag†
mm
Mask Register select
ddd
Selected destination
vvv
Validity setting for Memory Location
destinations
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction changes
it or a reset occurs. The default destination for Data Write
cycles is the Comparand register after a reset. When the
destination is the Comparand register or the memory array,
the data written may be masked by either Mask Register 1
or Mask Register 2, so that only destination bits
corresponding to bits in the mask register set to 0 will be
modified. An automatic compare will occur after writing
the last segment of the Comparand or mask registers, but
not after writing to memory. Setting the persistent
destination to M@aaaH loads the Address register with
“aaaH,” and the first access to that persistent destination
will be at aaaH, after which the AR value increments or
decrements as set in the Control register. The SPD M@[AR]
instruction does the same except the current Address
Register value is used.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
The TCO instruction selects a register as the source or
destination for only the next Command Read or Write cycle,
so a value can be loaded or read out of the register.
Subsequent Command Read or Write Cycles revert to
reading the Status register and writing to the Instruction
decoder. All registers but the NF, PS, and PD can be written
to, and all can be read from. The Status register is only
available via non-TCO Command Read cycles. Reading the
PS register also outputs the Device ID on bits 15–4 as
shown in Table 11 on page 16.
11
Rev. 2
Share Link: 